THE JOY OF CIRCUITS Richard Schreier Jan. 9 2013 ANALOG DEVICES - - PowerPoint PPT Presentation

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ANALOG INTEGRATED THE JOY OF CIRCUITS Richard Schreier Jan. 9 2013 ANALOG DEVICES Todays Message Analog IC design taps many areas of expertise: physics, geometry, analysis, algorithms, modeling, . Creativity (= Fun) is

SLIDE 1

Richard Schreier

Jan. 9 2013

THE JOY OF CIRCUITS

ANALOG INTEGRATED ANALOG DEVICES

SLIDE 2

ANALOG DEVICES

Today’s Message

Analog IC design taps many areas of expertise:

physics, geometry, analysis, algorithms, modeling, …. ⇒ Creativity (= Fun) is possible at multiple levels

Three Examples

1 Circuit: String DAC Tricks 2 Algorithmic/Signal Processing: ∆Σ DAC 3 Physical: Layout of a current-mode DAC

SLIDE 3

ANALOG DEVICES

1. Resistor-String DAC

+ Simple. Ratiometric. Monotonic. – N-bit DAC requires 2N components Vref r r r V o m 3 ⁄ ( )V ref = m 0 1 2 3 , , , =

2-bit example:

N-bit digital input selects

ne of 2N equi-spaced

analog values

SLIDE 4

ANALOG DEVICES

String DAC with Sub-String

Vref Vo + Number of units grows as 2N / 2 + Monotonic + Can repeat

sub-sub-string, etc.

– Needs buffers to prevent sub-string from loading the main string

Or does it?

SLIDE 5

ANALOG DEVICES

Unbuffered Sub-String

Vref Vo r r r r r r r 1 1 1

Choose the resistor ratio r

such that shifting the sub- string up one step increases the voltage at the common point by 1 LSB

Note that the voltages

elsewhere in the string are unaffected

[Dennis Dempsey US5969657]

SLIDE 6

ANALOG DEVICES

Required Resistor Ratio

+ – 1V r r + – 1V + – 1V 1 1 1 r r + – 4V 1 1 1 4 r

r

3     = r 1 = 4 3 r + = Solution: + – 3V

regardless of

the number of units in the sub-string! r 1 =

SLIDE 7

ANALOG DEVICES

More String Cleverness

Vref Vo R R R

Walk the sub-string up the

main string in an alternating fashion rather than shift it

ne step at a time

⇒ The number of switches on the main string is halved R R R R R R R

SLIDE 8

ANALOG DEVICES

2. Delta-Sigma (∆Σ) DAC
Suppose you have a fast and accurate, but

limited-resolution DAC Q1: How can you get more resolution? OR Q2: How can you get an output that is between two DAC levels?

DAC

8 Desired DAC Output Time Outputs

SLIDE 9

ANALOG DEVICES

Switch back and forth quickly; Average with a lowpass filter

High-resolution low-speed data

DAC

High-speed clock 16 8 16-b Input Data 8-b DAC Data Time

?

LPF

LPF Output

SLIDE 10

ANALOG DEVICES

One Digital Block

The decision to quantize high/low is made

independently of any previous decision

Turns the truncation noise into white noise

spread uniformly over frequency

?

16 8 16 8 8 8 dither spanning

ne 8-bit LSB

LSBs MSBs 16

SLIDE 11

ANALOG DEVICES

The ∆Σ Way

Re-circulate the LSBs to bias the next decision

16 8 8 @50 kHz @ 5 MHz 16-b Input Data 8-b DAC Data Time z–1

SLIDE 12

ANALOG DEVICES

Spectral Implications

Truncation noise is still spread over a broad

frequency range, but not uniformly

Very little noise is present in the signal band!

⇒ With the ∆Σ technique, a low-resolution DAC can be turned into a high-resolution DAC Freq. 25 kHz 2.5 MHz Desired Signal Shaped Noise

SLIDE 13

ANALOG DEVICES

3. Debugging

Where circuits designed in the virtual world collide with reality

One of the most important and instructive

aspects of analog IC work

Consider a current-mode DAC:

Need each leg to carry the same current as the master NMOS to within, say, 1%

Iout = m•Iin Iin = 1 mA 100 current sources

SLIDE 14

ANALOG DEVICES

Measurement Result— Disaster!

Iin

Current per leg Leg number 0 10 20 30 40 50 60 70 80 90 100 20% Error!

WHY?

SLIDE 15

ANALOG DEVICES

The Circuit Layout

… … 1 mA 0.8 mA

SLIDE 16

ANALOG DEVICES

Aha!

Wiring Resistance

r r r r r r I I I I

SLIDE 17

ANALOG DEVICES

Analysis

– ∆V + ∆I gm∆V = ∆V n2 2 ⁄ ( )rI = r r r r r r I I I I I–∆I n 100 = gm 2 mA/V = r 20 mΩ = ∆V 0.1 V = ∆I 0.2 mA = I 1 mA =

SLIDE 18

ANALOG DEVICES

How To Fix This Problem?

To get 20x better matching, need

Good luck with that.

Hopeless?

r 1 mΩ <

SLIDE 19

ANALOG DEVICES

Tree Connection

SLIDE 20

ANALOG DEVICES

Summary

Peeked at 3 examples of analog IC cleverness

Circuit-level: clever architecture Signal-processing: clever algorithm Physical-level: clever layout geometry

Innovation exists at many more levels and in

various combinations

There is still fresh ground to explore and exploit

The bulldozer that is digital CMOS is blazing a trail into new territory, enabling techniques that were impractical with earlier technologies. E.g. Reliance on digital signal processing; using time intervals to represent analog quantities.

Richard Schreier

THE JOY OF CIRCUITS

ANALOG INTEGRATED ANALOG DEVICES

Today’s Message

physics, geometry, analysis, algorithms, modeling, …. ⇒ Creativity (= Fun) is possible at multiple levels

Three Examples

1 Circuit: String DAC Tricks 2 Algorithmic/Signal Processing: ∆Σ DAC 3 Physical: Layout of a current-mode DAC

+ Simple. Ratiometric. Monotonic. – N-bit DAC requires 2N components Vref r r r V o m 3 ⁄ ( )V ref = m 0 1 2 3 , , , =

2-bit example:

analog values

String DAC with Sub-String

Vref Vo + Number of units grows as 2N / 2 + Monotonic + Can repeat

sub-sub-string, etc.

– Needs buffers to prevent sub-string from loading the main string

Or does it?

Unbuffered Sub-String

Vref Vo r r r r r r r 1 1 1

such that shifting the sub- string up one step increases the voltage at the common point by 1 LSB

elsewhere in the string are unaffected

[Dennis Dempsey US5969657]

Required Resistor Ratio

+ – 1V r r + – 1V + – 1V 1 1 1 r r + – 4V 1 1 1 4 r

r

3

    = r 1 = 4 3 r + = Solution: + – 3V

the number of units in the sub-string! r 1 =

More String Cleverness

Vref Vo R R R

main string in an alternating fashion rather than shift it

⇒ The number of switches on the main string is halved R R R R R R R

limited-resolution DAC Q1: How can you get more resolution? OR Q2: How can you get an output that is between two DAC levels?

DAC

8 Desired DAC Output Time Outputs

Switch back and forth quickly; Average with a lowpass filter

High-resolution low-speed data

DAC

High-speed clock 16 8 16-b Input Data 8-b DAC Data Time

?

LPF

LPF Output

One Digital Block

independently of any previous decision

spread uniformly over frequency

?

16 8 16 8 8 8 dither spanning

LSBs MSBs 16

The ∆Σ Way

16 8 8 @50 kHz @ 5 MHz 16-b Input Data 8-b DAC Data Time z–1

Spectral Implications

frequency range, but not uniformly

⇒ With the ∆Σ technique, a low-resolution DAC can be turned into a high-resolution DAC Freq. 25 kHz 2.5 MHz Desired Signal Shaped Noise

Where circuits designed in the virtual world collide with reality

aspects of analog IC work

Need each leg to carry the same current as the master NMOS to within, say, 1%

Iout = m•Iin Iin = 1 mA 100 current sources

Measurement Result— Disaster!

Iin

Current per leg Leg number 0 10 20 30 40 50 60 70 80 90 100 20% Error!

WHY?

The Circuit Layout

… … 1 mA 0.8 mA

Aha!

Wiring Resistance

r r r r r r I I I I

Analysis

– ∆V + ∆I gm∆V = ∆V n2 2 ⁄ ( )rI = r r r r r r I I I I I–∆I n 100 = gm 2 mA/V = r 20 mΩ = ∆V 0.1 V = ∆I 0.2 mA = I 1 mA =

How To Fix This Problem?

Good luck with that.

r 1 mΩ <

Tree Connection

Summary

Circuit-level: clever architecture Signal-processing: clever algorithm Physical-level: clever layout geometry

various combinations

The bulldozer that is digital CMOS is blazing a trail into new territory, enabling techniques that were impractical with earlier technologies. E.g. Reliance on digital signal processing; using time intervals to represent analog quantities.

⇒ Analog IC design provides good entertainment