Timing Sign-off for Selective Voltage Binning Vladimir Zolotov*, - - PowerPoint PPT Presentation

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Timing Sign-off for Selective Voltage Binning

Vladimir Zolotov*, Eric Foreman, Jeffrey Hemmett, Natesan Venkateswaran, Chandu Visweswariah*

IBM Electronic Design Automation, USA *IBM T. J. Watson Research Center, USA

March 6-7, 2014 TAU 2014, Santa Cruz, California, USA

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Outline

• Motivation
• Selective voltage binning and its benefits
• Timing sign-off criteria
• Small number of bins
• Large number of bins
• Nonseprability of Vdd variations
• Experimental results
• Conclusions

3

Motivation

• Vdd affects performance and

leakage

– Higher Vdd – higher leakage and higher performance

• Some chips are too leaky but

fast

– Lower Vdd makes leakage acceptable

• Some chips are too slow but

have small leakage

– Higher Vdd makes performance acceptable

• Adjusting Vdd improves yield

F Ioff Freq

too leaky too slow Vdd reduction Vdd increase

Imax

Good

4

Selective Voltage Binning (SVB)

• Chips are distributed among bins according to speed of transistors
• Each bin is assigned its own supply voltage to make chips sufficiently fast

Process Fast Slow Nominal PDF(Process) Vdd Process Slow Fast

5

Performance and power improvement by SVB

Without SVB: With SVB: Nom

High VDD

Dynamic Power Leakage

Low VDD High VDD

Delay

Dynamic Power Leakage

Power Process

Fast Fast Slow Slow

Process Power

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Timing Sign-off with SVB: Problem Formulation

• Check that chips can be manufactured

with required yield if they are assigned Vdd according to their voltage bins

– Take into account that interconnect wires and transistors have independent variations

• Worst case combinations of transistor

and interconnect variations are low probable

• Difficult problem for deterministic

timing

– Requires checking corners of each voltage bin

• Increases number of timing runs

manifold

– Cannot get timing credit for independence of transistor and interconnect variations

• Statistical timing covers whole

variational space in single run

– Uses functional representation of variability

• Slack at each point of variational

space can be computed by simple function

Process Vdd Fast Slow

R a X a P a V a s S

R i n i i P V

Δ + Δ + Δ + Δ + =

∑

=1

Bin1 Bin2 Bin3 Bin4 Whole Vdd/Process Variational space Sensitivities Sources of variations Variational space of voltage bins

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Timing Sign-Off

• Timing sign-off criterion is timing slack

– Setup slack is convenient metric of chip performance

• Statistical timing computes slack in canonical form

– Not a single number

• Incompatible with conventional sign-off methodology
• Projection transforms statistical slack into single number

– Deterministic (worst case) projection – Statistical projection (RSSIng)

• Corresponds to 3 sigma (99.87%) yield

– Combined projection

• Projected statistical slack makes statistical timing

compatible with conventional sign-off methodology

• Timing reports in conventional form

R a X a s S

R i n i i

Δ + Δ + =

∑

=1

⎟ ⎠ ⎞ ⎜ ⎝ ⎛ + − =

∑

=

| | | | 3

1 R n i i

a a s S

2 1 2

3

R n i i

a a s S + − =

∑

= 2 1 2 1

3 | | 3

R q k k m j j

a a a s S + − ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ − =

∑ ∑

= =

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Small number of bins: problem formulation

• Intra-bin variations are too large to be neglected

– Each bin covers wide range of variations

• Intra-bin process variation has truncated Gaussian distribution
• Statistical timing computes statistical slack covering variations

across all bins

• Compute and check projected slack for bin corners

– Faster than timing for bin corners

• Guarantee having 3 sigma (99.87%) yield of each bin

– Results in the same slack for all manufactured chips

• Combine process and interconnect variations statistically

– RSSing of process and interconnect variations

GT

X Δ

) (

GT

X p Δ

i-th bin

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Truncated Gaussian projection

• RSS sum of Gaussians

parameters into

• Truncate

– Filter out chips with

• utside truncation region
• Convolve truncated Gaussian

and Gaussians RSSed

• Project the resulted distribution

to 99.87% level

– Equivalent to 3 sigma Gaussian projection

• Use projection tables for fast

computation of multiple slacks in timing reports

( ) ( )

%) 87 . 99 (

2 2 1 1 tg GT GT n n GT GT

t t Y a X a t X a X a X a X a t T + ⇒ Δ + Δ + ⇒ Δ + + Δ + Δ + Δ + =

• Truncation

Others Gaussian parm-s

RSS List

Gaussian

Convolution

to be truncated

GT

X Δ

Truncated parameter Convolution

GT GT X

a Δ

GT GT X

a Δ

Y aΔ

99.87%

GT

X Δ

Projected value ttg

Y aΔ

Distribution of other parameters

Y aΔ τ τ φ τ d t ft ) ( ) ( −

∫

∞ ∞ −

) 3 ( ) (

1 − ∞ −

Φ =

∫

dt t f

tg

t

Compute ttg from tl tr

n n X

a X a X a Δ + + Δ + Δ

• 2

2 1 1

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SVB with small number of bins: implementation

Computation of truncation projection tables

• Mapping:
• Each table is characterized

with left and right truncation limits tl and tr

• Table input : sensitivity to

truncated variable b

• Table output: truncated

projected value ttg

• Tables are generated once for

technology node

– Does not affect timing run time

• Table access time does not

depend on table size

– Fixed step of input parameter

Projection slack computation

• Transform statistical slack to

form suitable for table application

• Find table with required

truncation limits tl and tr

• Compute projection by table

look up

• Compute projected slack

Y X b

GT

Δ + Δ

tg

t

n n GT GT

X a X a X a s Δ + + Δ + Δ +

• 1

1

( )

Y a X a s

GT GT

Δ + Δ +

( )

Y X b a s

GT

Δ + Δ +

tg

t

tg pr

t a s S ⋅ + =

Bin ranging from tl=-3 to tr=0 sigmas Sensitivity to truncated variable xx xx xx Projected truncated value xx xx xx

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SVB sign-off for large number of bins

• Projection of all process corners

is too inefficient

– Too many bins, too many corners

• Bins are very small

– Intra-bin variation of Vdd and Process is small

• Can be neglected

– Vdd and Process are almost perfectly (mis-) track each other

• Timing uses (anti-)correlation

between Process and Vdd to model SVB

– Simple and efficient solution – No need for multicorner projection – As Vdd perfectly tracks Process it became a random variable

• Same solution for adaptive

voltage supply

Process Vdd Fast Slow

R a X a P a V a s S

R i n i i P V

Δ + Δ + Δ + Δ + =

∑

=1

Anti-correlation Intra-bin variation

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SVB with multiple Vt families

• Variations of Vt families are correlated
• However, chip sorting among bins uses only Vt family
• Projection based timing sign-off assumed independence of SVB

variable

– Decorrelation is needed

• PCA is not suitable as decorrelated variables are not measured
• Decorrelation can be performed as follows:
• Each variable can be represented as

where

– is independent of

• Covariance

Therefore

• Variance of is

Therefore

• Applying this transformation to canonical form we remove correlation

between SVB variable and other variables

– Truncated Gaussian projection can be applied to SVB variable

… , , ,

2 1

P P P Δ Δ Δ

C i I i c i c i i i

a P P a E P a E P P E

, , , 2 ,

) ( ) ( ) , ( = Δ Δ + Δ = Δ Δ = ρ

I i I i c i i

P a P a P

, . ,

Δ + Δ = Δ

i

P Δ

P Δ

1 ) ( ) (

2 , 2 , 2

= + = Δ = Δ

I i C i i i

a a P E P Var

i

P Δ

I i

P, Δ P Δ

i C i

a ρ =

, 2 ,

1

i I i

a ρ − =

P Δ

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Nonseparable voltage variability

• Circuits are designed for wide range of

voltages

– Applications, voltage binning, adaptive voltage supply, dynamic voltage scaling

• Supply voltage is not statistical but

deterministic variable

– Must be modeled accurately in its entire range

• Supply voltage affects delay variability

– Linear model is too inaccurate

• Conventional statistical timing cannot

model voltage variations

– Large error occurs even at corners

• Existing solutions:

– Either single statistical timing run with additional design margins – Or 2 statistical timing runs at low and high voltages

• Both solutions are not sufficiently good

– Sign-of timing iterates between high and low voltages

Error of linear model Linear delay model Actual delay

V X D(V,X)

10.00% 12.00% 14.00% 16.00% 18.00% 20.00% 22.00% 24.00% 26.00% 28.00% 30.00% 0.7 0.75 0.8 0.85 0.9 0.95 1 1.05 1.1 1.15 UVT SVT HVT

Delay sensitivity to process Vdd

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Modeling deterministic nonseparable variations of Vdd

• Timing quantity is modeled with bi-linier form (hyperboloid)

– Voltage cross-terms model voltage influence on variability

• Supply voltage is modeled deterministically

– Fits voltage corners exactly

• Projection to voltage values turns bi-linear form into a linear one

ΔVΔY d ΔY d ΔV d d Y) D(V,

VY Y V

+ + + = ΔY d d (Y) D

LV Y, LV 0, LV

+ = ΔY d d (Y) D

HV Y, HV 0, HV

+ =

Low voltage model High voltage model DHV(Y) DLV(Y)

Y V

ΔY d d (Y) D

V Y, V 0, V

+ =

Mid voltage model

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SVB for requirement of two voltage levels

• Binned chips are often required to function at high Vdd as well

– Testing, reading setup information, setup, etc.

• Vdd variation is not fully correlated with process
• Linear statistical timing is inaccurate for modeling deterministic Vdd

variations and its impact of other variations

• Simple solution requires two timing runs:

– Vdd=Vmax and Vdd correlated with Process

• Better solution is statistical timing run with bilinear canonical forms

– Cross-terms model Vdd impact on other variations – Worst slack occurs on lines 1-2 and 3-4

• Projection to line 3-4 is simple as Vdd=const on that line

VDDlowmin

Process

VDDmax VDDmin Fast Slow Nom

VDD

2 3 4 1

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Projection to oblique line of variability region

• Slack
• On oblique line
• Statistical projection of slack as function of
• Worst slack is computed as

– Where achieved inside

• is computed by solving equation for derivative

V Δ

) ), ( ), ( min(

min min min

S V S V S S

low W

Δ Δ =

[ ]

min min, V

Vlo Δ Δ

∑ ∑

= =

Δ Δ + Δ + Δ Δ + Δ + Δ −

n i i V i n i i i PV P V

X V a X a P V a P a V a s

1 , 1 I C

V V V Δ + Δ ⇒ Δ P VC Δ = Δ

Split VDD where

∑ ∑

= =

Δ Δ + Δ + Δ Δ + Δ − + Δ −

n i i V i n i i i PV VC P I VI

X V a X a P V a P a a V a s

1 , 1

) (

min min low

V V V Δ ≤ Δ ≤ Δ

∑ ∑

= =

Δ + + Δ + − − Δ − = Δ

n i V i n i i PV VC P I VI

V a a V a a a V a s V S

1 2 2 , 1 2 2 2 2

) ( 3 ) (

( )

) ( min

min

V S S Δ =

( )

) ( min

min

V S S Δ =

) ( = Δ ∂ Δ ∂ V V S

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Timing of 2 bin SVB, 16 bin SVB and no SVB

Experiment Setup Test Hold Test Violations Worst Slack Impr-ment Violations Worst Slack Impr-ment Impr-ment Impr-ment Max:Avr:Min Impr-ment Impr-ment Max:Avr:Min Low Vdd 88933

• 2112

n/a 44832

• 1417

n/a High Vdd 7329

• 1894

n/a 47824

• 1286

n/a 2bin low V 68056

• 2079 333 : 100.6

43774

• 1357 87 : 36

20877 33 -17 1058 60 -18 2bin high V 6315

• 1855 209 : 32

46231

• 1275 87 : 15.9

1014 39 -6 1593 11 -13 16bin low V 44550

• 2074 426 : 119

41760

• 1361 114 : 37

44383 38 -4 3072 56 -11 16bin high V 5417

• 1853 384 : 53

42779

• 1242 97 : 30

1912 41 4 5025 43 -1

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Histogram of slack improvement by SVB

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Timing slack of 16 bin SVB vs. low Vdd

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Conclusions

• Developed methods of timing sign-off for selective voltage binning

and adaptive voltage supply

– Statistical timing helps to avoid multiple timing runs

• Significant reduction of total run time
• Only one timing report to analyze

– Projection of statistical slack makes statistical timing sign-off similar to conventional methodology

• Timing reports are similar to deterministic approach
• Cases of small and large number of bins are considered separately

– For better tradeoff between run time and accuracy

• SVB timing was extended to modeling nonseparable Vdd variations

– Support of requirements for chips to function at high Vdd

• Developed techniques were used for timing sign-off for 3 technology

nodes: 65, 45 and 32nm

– Timing yield improvement – Lowering timing requirements – Simplified timing closure – Design cycle reduction