Transaction-Level Models of Systems-on-a-Chip Can they be Fast, - - PowerPoint PPT Presentation

SoCs and TLM Compilation Verification Extra-functional Conclusion

Transaction-Level Models of Systems-on-a-Chip Can they be Fast, Correct and Faithful?

Matthieu Moy

Laboratoire d’Informatique du Parallelisme Lyon, France

February 2018

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 1 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

About me

2005

• Ph.D: formal verification of SoC models (ST/Verimag)

2006

• Post-doc: security of storage (Bangalore, Inde)

2006

• Assistant professor, Verimag / Ensimag

Work on SoC models & abstract interpretation 2014

• HDR: High-Level models for Embedded Systems

2017

• New CASH team leader, LIP / UCBL

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 2 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Outline

1

Introduction: Systems-on-a-Chip, Transaction-Level Modeling

2

Compilation of SystemC/TLM

3

Verification of SystemC/TLM

4

Extra-Functional Properties in TLM

5

Conclusion

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 3 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Outline

1

Introduction: Systems-on-a-Chip, Transaction-Level Modeling

2

Compilation of SystemC/TLM

3

Verification of SystemC/TLM

4

Extra-Functional Properties in TLM

5

Conclusion

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 3 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Modern Systems-on-a-Chip

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 4 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Modern Systems-on-a-Chip

Software Hardware

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 4 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Hardware/Software Design Flow

Time Traditional Design-Flow

Specification, Algorithm RTL Design Synthesis Factory Software Development Integration Validation

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 5 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Hardware/Software Design Flow

Time Traditional Design-Flow

Specification, Algorithm RTL Design Synthesis Factory Software Development Integration Validation cost > 1,000,000 $ !

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 5 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Hardware/Software Design Flow

Time Traditional Design-Flow

Specification, Algorithm RTL Design Synthesis Factory Software Development Integration Validation

Transaction-Level Model based

Specification, Algorithm RTL Design Synthesis

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 5 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Hardware/Software Design Flow

Time Traditional Design-Flow

Specification, Algorithm RTL Design Synthesis Factory Software Development Integration Validation

Transaction-Level Model based

Specification, Algorithm RTL Design Synthesis Software Development

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 5 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Hardware/Software Design Flow

Time Traditional Design-Flow

Specification, Algorithm RTL Design Synthesis Factory Software Development Integration Validation

Transaction-Level Model based

Specification, Algorithm RTL Design Synthesis Software Development TLM Model

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 5 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Hardware/Software Design Flow

Time Traditional Design-Flow

Specification, Algorithm RTL Design Synthesis Factory Software Development Integration Validation

Transaction-Level Model based

Specification, Algorithm RTL Design Synthesis Software Development TLM Model Integration Factory Validation

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 5 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Hardware/Software Design Flow

Time Traditional Design-Flow

Specification, Algorithm RTL Design Synthesis Factory Software Development Integration Validation

Transaction-Level Model based

Specification, Algorithm RTL Design Synthesis Software Development TLM Model Integration Factory Validation

gain

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 5 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

The Transaction Level Model: Principles and Objectives A high level of abstraction, that appears early in the design-flow

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 6 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

The Transaction Level Model: Principles and Objectives A high level of abstraction, that appears early in the design-flow

A virtual prototype of the system, to enable

◮ Early software development ◮ Integration of components ◮ Architecture exploration ◮ Reference model for validation

Abstract implementation details from RTL

◮ Fast simulation (≃ 1000x faster than RTL) ◮ Lightweight modeling effort (≃ 10x less than RTL) Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 6 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Content of a TLM Model

A first definition

Model what is needed for Software Execution:

◮ Processors ◮ Address-map ◮ Concurrency

... and only that.

◮ No micro-architecture ◮ No bus protocol ◮ No pipeline ◮ No physical clock ◮ . . . Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 7 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

An example TLM Model

TLM Bus CPU process = C++ code ITC Data RAM Instruction RAM GPIO VGA Timer

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 8 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Performance of TLM

x60 x20 Simulation time (second) logarithmic scale 10000 100 10 1 x3 HW emulation RTL + cosimulation TLM Pure RTL 1 hour 3 minutes 3 seconds 1 second

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 9 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Uses of Functional Models

Reference for Hardware Validation

SPEC

Virtual Prototype for Software Development

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 10 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Uses of Functional Models

Reference for Hardware Validation

SPEC

RTL

?

=

Virtual Prototype for Software Development

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 10 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Uses of Functional Models

Reference for Hardware Validation

SPEC

RTL

TLM

?

=

Virtual Prototype for Software Development

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 10 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Uses of Functional Models

Reference for Hardware Validation

SPEC

RTL

TLM

?

=

Virtual Prototype for Software Development

TLM

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 10 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Uses of Functional Models

Reference for Hardware Validation

SPEC

RTL

TLM

?

=

Virtual Prototype for Software Development

TLM

Unmodified Software

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 10 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Uses of Functional Models

Reference for Hardware Validation

SPEC

RTL

TLM

?

=

Virtual Prototype for Software Development

TLM

Unmodified Software

?

⊇

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 10 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Content of a TLM Model

A richer definition

Timing information

◮ May be needed for Software Execution ◮ Useful for Profiling Software

Power and Temperature

◮ Validate design choices ◮ Validate power-management policy

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 11 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Use of Extra-Functional Models

Timing, Power consumption, Temperature Estimation

TLM

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 12 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Use of Extra-Functional Models

Timing, Power consumption, Temperature Estimation

TLM

Estimated

Actual

?

≈

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 12 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Use of Extra-Functional Models

Timing, Power consumption, Temperature Estimation

TLM

Estimated

Actual

?

≈

Unmodified Power/Temperature-Aware Software

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 12 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Summary: Expected Properties of TLM Programs

SystemC/TLM Programs should Simulate fast, Satisfy correctness criterions, Reflect faithfully functional and extra-functional properties of the actual system.

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 13 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Outline

1

Introduction: Systems-on-a-Chip, Transaction-Level Modeling

2

Compilation of SystemC/TLM

3

Verification of SystemC/TLM

4

Extra-Functional Properties in TLM

5

Conclusion

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 13 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

SystemC: Simple Example

N1 N2

SC_MODULE(not_gate) { sc_in<bool> in; sc_out<bool> out; void compute (void) { // Behavior bool val = in.read();

• ut.write(!val);

} SC_CTOR(not_gate) { SC_METHOD(compute); sensitive << in; } }; int sc_main(int argc, char **argv) { // Elaboration phase (Architecture) // Instantiate modules ... not_gate n1("N1"); not_gate n2("N2"); sc_signal<bool> s1, s2; // ... and bind them together n1.out.bind(s1); n2.out.bind(s2); n1.in.bind(s2); n2.in.bind(s1); // Start simulation sc_start(100, SC_NS); return 0; }

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 14 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Compiling SystemC

$ g++ example.cpp -lsystemc $ ./a.out ... end of section?

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 15 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Compiling SystemC

$ g++ example.cpp -lsystemc $ ./a.out

But ... C++ compilers cannot do SystemC-aware optimizations C++ analyzers do not know SystemC semantics

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 15 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

This section

2

Compilation of SystemC/TLM Front-end Optimization and Fast Simulation

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 15 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

SystemC Front-End

In this talk: Front-end = “Compiler front-end” (AKA “Parser”) SystemC Front end Intermediate Representation Back end Intermediate Representation = Architecture + Behavior

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 16 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

SystemC Front-Ends

When you don’t need a front-end:

◮ Main application of SystemC: Simulation ◮ Testing, run-time verification, monitoring. . . Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 17 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

SystemC Front-Ends

When you don’t need a front-end:

◮ Main application of SystemC: Simulation ◮ Testing, run-time verification, monitoring. . .

⇒ No reference front-end available on http://www.accellera.org/

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 17 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

SystemC Front-Ends

When you don’t need a front-end:

◮ Main application of SystemC: Simulation ◮ Testing, run-time verification, monitoring. . .

⇒ No reference front-end available on http://www.accellera.org/ When you do need a front-end:

◮ Symbolic formal verification, High-level synthesis ◮ Visualization ◮ Introspection ◮ SystemC-specific Compiler Optimizations ◮ Advanced debugging features Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 17 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Challenges and Solutions with SystemC Front-Ends

1

C++ is complex (e.g. clang ≈ 200,000 LOC)

2

Architecture built at runtime, with C++ code

SC_MODULE(not_gate) { sc_in<bool> in; sc_out<bool> out; void compute (void) { // Behavior bool val = in.read();

• ut.write(!val);

} SC_CTOR(not_gate) { SC_METHOD(compute); sensitive << in; } }; int sc_main(int argc, char **argv) { // Elaboration phase (Architecture) not_gate n1("N1"); not_gate n2("N2"); sc_signal<bool> s1, s2; // Binding n1.out.bind(s1); n2.out.bind(s2); n1.in.bind(s2); n2.in.bind(s1); // Start simulation sc_start(100, SC_NS); return 0; }

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 18 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Challenges and Solutions with SystemC Front-Ends

1

C++ is complex (e.g. clang ≈ 200,000 LOC) Write a C++ front-end or reuse one (g++, clang, EDG, . . . )

2

Architecture built at runtime, with C++ code Analyze elaboration phase or execute it

SC_MODULE(not_gate) { sc_in<bool> in; sc_out<bool> out; void compute (void) { // Behavior bool val = in.read();

• ut.write(!val);

} SC_CTOR(not_gate) { SC_METHOD(compute); sensitive << in; } }; int sc_main(int argc, char **argv) { // Elaboration phase (Architecture) not_gate n1("N1"); not_gate n2("N2"); sc_signal<bool> s1, s2; // Binding n1.out.bind(s1); n2.out.bind(s2); n1.in.bind(s2); n2.in.bind(s1); // Start simulation sc_start(100, SC_NS); return 0; }

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 18 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Challenges and Solutions with SystemC Front-Ends

1

C++ is complex (e.g. clang ≈ 200,000 LOC) Write a C++ front-end or reuse one (g++, clang, EDG, . . . )

2

Architecture built at runtime, with C++ code Analyze elaboration phase or execute it

SC_MODULE(not_gate) { sc_in<bool> in; sc_out<bool> out; void compute (void) { // Behavior bool val = in.read();

• ut.write(!val);

} SC_CTOR(not_gate) { SC_METHOD(compute); sensitive << in; } }; int sc_main(int argc, char **argv) { // Elaboration phase (Architecture) not_gate n1("N1"); not_gate n2("N2"); sc_signal<bool> s1, s2; // Binding n1.out.bind(s1); n2.out.bind(s2); n1.in.bind(s2); n2.in.bind(s1); // Start simulation sc_start(100, SC_NS); return 0; } Static Approaches Dynamic Approaches

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 18 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Dealing with the architecture

When it becomes tricky. . .

int sc_main(int argc, char **argv) { int n = atoi(argv[1]); int m = atoi(argv[2]); Node array[n][m]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { array[i][j] = new Node(...); ... } } sc_start(100, SC_NS); return 0; }

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 19 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Dealing with the architecture

When it becomes tricky. . .

Static approach: cannot deal with such code Dynamic approach: can extract the architecture for individual instances of the system

int sc_main(int argc, char **argv) { int n = atoi(argv[1]); int m = atoi(argv[2]); Node array[n][m]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { array[i][j] = new Node(...); ... } } sc_start(100, SC_NS); return 0; }

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 19 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Dealing with the architecture

When it becomes very tricky. . .

void compute(void) { for (int i = 0; i < n; i++) { ports[i].write(true); } ... }

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 20 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Dealing with the architecture

When it becomes very tricky. . .

One can unroll the loop to let i become constant, Undecidable in the general case.

void compute(void) { for (int i = 0; i < n; i++) { ports[i].write(true); } ... }

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 20 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

The beginning: Pinapa

AKA “my Ph.D’s front-end”

Pinapa’s principle:

◮ Use GCC’s C++ front-end ◮ Compile, dynamically load and execute the elaboration (sc_main)

Pinapa’s drawbacks:

◮ Uses GCC’s internals (hard to port to newer versions) ◮ Hard to install and use, no separate compilation ◮ Ad-hoc match of SystemC constructs in AST ◮ AST Vs SSA form in modern compilers Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 21 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

LLVM: Low Level Virtual Machine

Bitcode Front ends Back ends C C++ ... Optimizer JIT compilation Code Generation Clean API Clean SSA intermediate representation Many tools available

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 22 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

LLVM: Low Level Virtual Machine

Bitcode Front ends Back ends C C++ ... Optimizer JIT compilation Code Generation Clean API Clean SSA intermediate representation Many tools available

Can we be here? Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 22 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

PinaVM: Enriching the bitcode

SystemC Compilation (llvm-g++, llvm-link) LLVM bitcode Execute elaboration Architecture Identify SC constructs bitcode++ Intermediate Representation Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 23 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

PinaVM: Enriching the bitcode

SystemC Compilation (llvm-g++, llvm-link) LLVM bitcode Execute elaboration Architecture Identify SC constructs bitcode++ Intermediate Representation Execute dependencies

... %port = expr1(%this) %data = expr2 SCWrite

• data = ??
• port = ??

...

SystemC construct is still a normal function %this is fixed %this not known Cannot compute %port

... port.write(data); ... ... %port = expr1(%this) %data = expr2 call write %port, %data ... ... %port = expr1(%this) %data = expr2 SCWrite

• data =
• Process 0 → data d0

Process 1 → data d1

• port =

Process 0 → port p0 Process 1 → port p1

• ...

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 23 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Summary

PinaVM relies on executability (JIT Compiler) for execution of:

◮ elaboration phase (≈ like Pinapa) ◮ sliced pieces of code

Open Source: http://forge.imag.fr/projects/pinavm/ Still a prototype, but very few fundamental limitations ≈ 3000 lines of C++ code on top of LLVM Experimental back-ends for

◮ Execution (Tweto) ◮ Model-checking (using SPIN) Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 24 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

This section

2

Compilation of SystemC/TLM Front-end Optimization and Fast Simulation

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 24 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Typical Transaction Journey

Bus CPU RAM T1 T2 0x0000 0x1000 T1 0x2000 0x3000 T2 0x5000 0x6000 RAM

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 25 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Typical Transaction Journey

Bus CPU RAM T1 T2 0x0000 0x1000 T1 0x2000 0x3000 T2 0x5000 0x6000 RAM

...

port.write(addr,data); ... status write(addr,data) { mem[addr] = data; }

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 25 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Typical Transaction Journey

Bus CPU RAM T1 T2 0x0000 0x1000 T1 0x2000 0x3000 T2 0x5000 0x6000 RAM

...

port.write(addr,data); ... status write(addr,data) { mem[addr] = data; } Call virtual method

• n socket

Forward method call to target socket Address Decoding Another virtual method call Forwarded to target socket

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 25 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Typical Transaction Journey

Bus CPU RAM T1 T2 0x0000 0x1000 T1 0x2000 0x3000 T2 0x5000 0x6000 RAM

...

port.write(addr,data); ... status write(addr,data) { mem[addr] = data; } Call virtual method

• n socket

Forward method call to target socket Address Decoding Another virtual method call Forwarded to target socket Ends-up calling target module’s method

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 25 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Typical Transaction Journey

Bus CPU RAM T1 T2 0x0000 0x1000 T1 0x2000 0x3000 T2 0x5000 0x6000 RAM

port.write(addr,data); ... status write(addr,data) { mem[addr] = data; } Call virtual method

• n socket

Forward method call to target socket Address Decoding Another virtual method call Forwarded to target socket Ends-up calling target module’s method

Many costly operations for a simple functionality Work-around: backdoor access (DMI = Direct Memory Interface)

◮ CPU get a pointer to RAM’s internal data ◮ Manual, dangerous optimization Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 25 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Typical Transaction Journey

Bus CPU RAM T1 T2 0x0000 0x1000 T1 0x2000 0x3000 T2 0x5000 0x6000 RAM

port.write(addr,data); ... status write(addr,data) { mem[addr] = data; } Call virtual method

• n socket

Forward method call to target socket Address Decoding Another virtual method call Forwarded to target socket Ends-up calling target module’s method

Many costly operations for a simple functionality Work-around: backdoor access (DMI = Direct Memory Interface)

◮ CPU get a pointer to RAM’s internal data ◮ Manual, dangerous optimization

Can a compiler be as good as DMI, automatically and safely?

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 25 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Basic Ideas

Do statically what can be done statically ... ... considering “statically” = “after elaboration” Examples:

◮ Virtual function resolution ◮ Inlining through SystemC ports ◮ Static address resolution Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 26 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Dealing with addresses Statically

Bus CPU RAM

...

port.write(0x5500,data); ... status write(addr,data) { mem[addr] = data; } 0x0000 0x1000 T1 0x2000 0x3000 T2 0x5000 0x6000 RAM

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 27 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Dealing with addresses Statically

Bus CPU RAM

...

port.write(0x5500,data); ... status write(addr,data) { mem[addr] = data; } 0x0000 0x1000 T1 0x2000 0x3000 T2 0x5000 0x6000 RAM Get actual port addr from PinaVM

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 27 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Dealing with addresses Statically

Bus CPU RAM

...

port.write(0x5500,data); ... status write(addr,data) { mem[addr] = data; } 0x0000 0x1000 T1 0x2000 0x3000 T2 0x5000 0x6000 RAM Get actual port addr from PinaVM Follow path to bus

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 27 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Dealing with addresses Statically

Bus CPU RAM

...

port.write(0x5500,data); ... status write(addr,data) { mem[addr] = data; } 0x0000 0x1000 T1 0x2000 0x3000 T2 0x5000 0x6000 RAM Get actual port addr from PinaVM Follow path to bus Address Decoding

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 27 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Dealing with addresses Statically

Bus CPU RAM

...

port.write(0x5500,data); ... status write(addr,data) { mem[addr] = data; } 0x0000 0x1000 T1 0x2000 0x3000 T2 0x5000 0x6000 RAM Get actual port addr from PinaVM Follow path to bus Address Decoding Find target socket at this address

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 27 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Dealing with addresses Statically

Bus CPU RAM

...

port.write(0x5500,data); ... status write(addr,data) { mem[addr] = data; } 0x0000 0x1000 T1 0x2000 0x3000 T2 0x5000 0x6000 RAM Get actual port addr from PinaVM Follow path to bus Address Decoding Find target socket at this address Find function in target module

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 27 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Dealing with addresses Statically

Bus CPU RAM

port.write(0x5500,data); ... status write(addr,data) { mem[addr] = data; } 0x0000 0x1000 T1 0x2000 0x3000 T2 0x5000 0x6000 RAM Get actual port addr from PinaVM Follow path to bus Address Decoding Find target socket at this address Find function in target module

Possible optimizations:

◮ Replace call to port.write() with RAM.write() ◮ Possibly inline it Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 27 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Outline

1

Introduction: Systems-on-a-Chip, Transaction-Level Modeling

2

Compilation of SystemC/TLM

3

Verification of SystemC/TLM

4

Extra-Functional Properties in TLM

5

Conclusion

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 27 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Encoding Approaches

SystemC Encoding Formal language Existing verifier Yes/No/Maybe

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 28 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Encoding Approaches

SystemC Concurrent program Synchronous automata + scheduler T1 × T2 × T3 × Sch Asynchronous automata T1 × T2 × T3 × Sch Asynchronous automata Dedicated product T1 × T2 × T3 Asynchronous product shared variable T1 × T2 × T3

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 29 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Encoding Approaches

SystemC Concurrent program Synchronous automata + scheduler T1 × T2 × T3 × Sch Asynchronous automata T1 × T2 × T3 × Sch Asynchronous automata Dedicated product T1 × T2 × T3 Asynchronous product shared variable T1 × T2 × T3

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 29 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Translating a SystemC Program

Translation = Parse the source code, generate an automaton Direct semantics = Read the specification, instantiate an automaton

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 30 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Translating a SystemC Program

Translation = Parse the source code, generate an automaton Direct semantics = Read the specification, instantiate an automaton

Scheduler

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 30 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Translating a SystemC Program

Translation = Parse the source code, generate an automaton Direct semantics = Read the specification, instantiate an automaton

Scheduler User code: Automatic translation

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 30 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Translating a SystemC Program

Translation = Parse the source code, generate an automaton Direct semantics = Read the specification, instantiate an automaton

Scheduler User code: Automatic translation SystemC kernel: Direct semantics

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 30 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Translating a SystemC Program

Translation = Parse the source code, generate an automaton Direct semantics = Read the specification, instantiate an automaton

Scheduler User code: Automatic translation SystemC kernel: Direct semantics Direct semantics Communication:

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 30 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

The SystemC scheduler

Non-preemptive scheduler Non-deterministic processes election Init Select process Run Update Time elapse (+ 1 automaton per process to reflect its state)

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 31 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Encoding Approaches

SystemC Concurrent program Synchronous automata + scheduler T1 × T2 × T3 × Sch Asynchronous automata T1 × T2 × T3 × Sch Asynchronous automata Dedicated product T1 × T2 × T3 Asynchronous product shared variable T1 × T2 × T3

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 32 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Encoding Approaches

SystemC Concurrent program Synchronous automata + scheduler T1 × T2 × T3 × Sch Asynchronous automata T1 × T2 × T3 × Sch Asynchronous automata Dedicated product T1 × T2 × T3 Asynchronous product shared variable T1 × T2 × T3

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 32 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Encoding Approaches

SystemC Concurrent program Synchronous automata + scheduler T1 × T2 × T3 × Sch Asynchronous automata T1 × T2 × T3 × Sch Asynchronous automata Dedicated product T1 × T2 × T3 Asynchronous product shared variable T1 × T2 × T3

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 32 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Encoding Approaches

SystemC Concurrent program Synchronous automata + scheduler T1 × T2 × T3 × Sch Asynchronous automata T1 × T2 × T3 × Sch Asynchronous automata Dedicated product T1 × T2 × T3 Asynchronous product shared variable T1 × T2 × T3

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 32 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

SystemC to Spin: encoding events

notify/wait for event Ek: p::wait(Ek): Wp := k blocked(Wp == 0) p::notify(Ek): ∀i ∈ P|Wi == K Wi := 0 Wp : integer associated to process p. Wp = k ⇔ “process p is waiting for event Ek”.

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 33 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

SystemC to Spin: encoding time and events

discrete time a deadline variable Tp is attached to each process p Tp = next execution time for process p p::wait(d): Tp := Tp + d blocked(Tp == min

i∈P (Ti))

“Set my next execution time to now + d and wait until the current execution time reaches it”

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 34 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

SystemC to Spin: encoding time and events

discrete time a deadline variable Tp is attached to each process p Tp = next execution time for process p p::wait(d): Tp := Tp + d blocked(Tp == min

i∈P Wi==0

(Ti)) “Set my next execution time to now + d and wait until the current execution time reaches it” p::wait(Ek): Wp := K blocked(Wp == 0) p::notify(Ek): ∀i ∈ P|Wi == K Wi := 0 Ti := Tp

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 34 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

SystemC to Spin: results

1e+06 2e+06 3e+06 4e+06 5e+06 6e+06 7e+06 2 4 6 8 10 12 14 16 18 20 22 Nb of states Nb of components PinaVM PinaVM [SPIN 07]

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 35 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Encoding Approaches

SystemC Concurrent program Synchronous automata + scheduler T1 × T2 × T3 × Sch Asynchronous automata T1 × T2 × T3 × Sch Asynchronous automata Dedicated product T1 × T2 × T3 Asynchronous product shared variable T1 × T2 × T3

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 36 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Outline

1

Introduction: Systems-on-a-Chip, Transaction-Level Modeling

2

Compilation of SystemC/TLM

3

Verification of SystemC/TLM

4

Extra-Functional Properties in TLM

5

Conclusion

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 36 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

This section

4

Extra-Functional Properties in TLM Time and Parallelism Power and Temperature Estimation

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 36 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Parallelization of Simulations

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 37 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Parallelization of Simulations

System-level Simulation Vs HPC

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 38 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Problems and solutions for parallel execution of SystemC/TLM

(1) Execution order imposed by SystemC semantics (2) Concurrent access to shared resources (e.g., x++ on a global variable)

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 39 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Problems and solutions for parallel execution of SystemC/TLM

(1) Execution order imposed by SystemC semantics (2) Concurrent access to shared resources (e.g., x++ on a global variable)

No 100% automatic and efficient solution for TLM

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 39 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Problems and solutions for parallel execution of SystemC/TLM

(1) Execution order imposed by SystemC semantics (2) Concurrent access to shared resources (e.g., x++ on a global variable)

No 100% automatic and efficient solution for TLM Our proposal = additional constructs: Desynchronization (1) / Synchronization (2)

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 39 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Approaches to parallelization

Efficient Targets a wide subset of SystemC Few/no modifications required

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 40 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

SC-DURING: The Idea

SC_THREAD_1 SC_THREAD_2 . . . SC_THREAD_N OS thread_1 OS thread_2 OS thread_N SystemC OS thread Unmodified SystemC Some computation delegated to other threads Weak synchronization between SystemC and threads thanks to tasks with duration

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 41 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Simulated Time Vs Wall-Clock Time

Simulated time

10 20 30 40

Wall-clock time Time elapse Computation

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 42 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Simulated Time in SystemC and SC-DURING

SystemC sc-during A B P Q

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 43 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Simulated Time in SystemC and SC-DURING

SystemC sc-during A B P Q Process A: // Computation f(); // Time taken by f wait(20); f() wait(20)

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 43 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Simulated Time in SystemC and SC-DURING

SystemC sc-during A B P Q Process A: // Computation f(); // Time taken by f wait(20); f() wait(20) Process P: g(); wait(20); g() wait(20)

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 43 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Simulated Time in SystemC and SC-DURING

SystemC sc-during A B P Q Process A: // Computation f(); // Time taken by f wait(20); f() wait(20) Process P: g(); wait(20); during(15, h); g() wait(20) h()

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 43 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Simulated Time in SystemC and SC-DURING

SystemC sc-during A B P Q Process A: // Computation f(); // Time taken by f wait(20); f() wait(20) Process P: g(); wait(20); during(15, h); g() wait(20) h() i() j()

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 43 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Impact on Parallelism

P1 P2 P3 P4

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 44 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Concurrency in an industrial platform

Number of SystemC threads active within a cycle (ST set-top-box case study) :

0 % 50 % 100 % boot+init mpeg2 h264 mpeg2 → h264 0 Proc. 1 2 3 4 and more

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 45 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Impact on Parallelism

P1 P2 P3 P4

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 46 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Impact on Parallelism

P1 P2 P3 P4

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 46 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Impact on Parallelism

P1 P2 P3 P4

Overlap between tasks parallel execution in sc-during

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 46 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Execution of during(T)

Slow computation

Simulated time

10 20 30 40

Wall-clock time Task starts Simulated time blocked Task finishes

Fast computation

Simulated time

10 20 30 40

Wall-clock time Task starts Computation ends Task finishes Rest of the platform drives time idle

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 47 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

SC-DURING: First (Naive) Implementation

void during(sc_core::sc_time d, std::function<void()> f) { 1 std::thread t(f); // Thread creation 2 sc_core::wait(d); // SystemC executes 3 t.join(); // Wait for completion } A B C Thread

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 48 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

SC-DURING: First (Naive) Implementation

void during(sc_core::sc_time d, std::function<void()> f) { 1 std::thread t(f); // Thread creation 2 sc_core::wait(d); // SystemC executes 3 t.join(); // Wait for completion } A B C Thread during(d, f);

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 48 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

SC-DURING: First (Naive) Implementation

void during(sc_core::sc_time d, std::function<void()> f) { 1 std::thread t(f); // Thread creation 2 sc_core::wait(d); // SystemC executes 3 t.join(); // Wait for completion } A B C Thread 1 during(d, f); création du thread f

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 48 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

SC-DURING: First (Naive) Implementation

void during(sc_core::sc_time d, std::function<void()> f) { 1 std::thread t(f); // Thread creation 2 sc_core::wait(d); // SystemC executes 3 t.join(); // Wait for completion } A B C Thread 1 during(d, f); création du thread f 2 wait(d)

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 48 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

SC-DURING: First (Naive) Implementation

void during(sc_core::sc_time d, std::function<void()> f) { 1 std::thread t(f); // Thread creation 2 sc_core::wait(d); // SystemC executes 3 t.join(); // Wait for completion } A B C Thread 1 during(d, f); création du thread f 2 wait(d)

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 48 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

SC-DURING: First (Naive) Implementation

void during(sc_core::sc_time d, std::function<void()> f) { 1 std::thread t(f); // Thread creation 2 sc_core::wait(d); // SystemC executes 3 t.join(); // Wait for completion } A B C Thread 1 during(d, f); création du thread f 2 wait(d) join() 3

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 48 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

SC-DURING: First (Naive) Implementation

void during(sc_core::sc_time d, std::function<void()> f) { 1 std::thread t(f); // Thread creation 2 sc_core::wait(d); // SystemC executes 3 t.join(); // Wait for completion } A B C Thread 1 during(d, f); création du thread f 2 wait(d) join() 3

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 48 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

SC-DURING: New Synchronization Primitives

extra_time(t): Increase duration of current task P wait(5) initial duration extra time

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 49 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

SC-DURING: New Synchronization Primitives

extra_time(t): Increase duration of current task P wait(5) initial duration extra time catch_up(): Wait for SystemC to reach the end of the task while (!c) { extra_time(10); catch_up(); // Ensures fairness }

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 49 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

SC-DURING: New Synchronization Primitives

extra_time(t): Increase duration of current task P wait(5) initial duration extra time catch_up(): Wait for SystemC to reach the end of the task while (!c) { extra_time(10); catch_up(); // Ensures fairness } sc_call(f): Call function f in the context of SystemC x++; // Forbidden in // sc-during task sc_call([]{ x++; }); // OK

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 49 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

SC-DURING: Implementations

SC_THREAD_1 SC_THREAD_2 . . . SC_THREAD_N sync_task_1 OS thread_1 sync_task_2 OS thread_2 sync_task_N OS thread_N SystemC OS Thread Strategies: SEQ Sequential (= reference) THREAD Thread creation + destruction for each task POOL Pre-allocated set of threads ONDEMAND Thread created on demand and reused

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 50 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

SC-DURING: Results

2 4 6 8 10 12 14 10 20 30 40 50 60

Speedup

Number of processors in the model

Loose timing

(explicit synchronization)

Fine-grained synchronization Test machine : 4 × 12 = 48 cores

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 51 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Addressing the Faithfulness Issue: Exposing Bugs

Example bug: mis-placed synchronization: imgReady = true; wait(5, SC_US); writeIMG(); wait(10, SC_US); || while(!imgReady) wait(1, SC_US); wait(10, SC_US); readIMG(); ⇒ bug never seen in simulation

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 52 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Addressing the Faithfulness Issue: Exposing Bugs

Example bug: mis-placed synchronization: imgReady = true; wait(5, SC_US); writeIMG(); wait(10, SC_US); || while(!imgReady) wait(1, SC_US); wait(10, SC_US); readIMG(); ⇒ bug never seen in simulation during(15, SC_US, []{ imgReady = true; writeIMG(); }); || while(!imgReady) wait(1, SC_US); wait(10, SC_US); readIMG(); ⇒ strictly more behaviors, including the buggy one

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 52 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Model Faithfulness

model actual

Extra behaviors

• f the model

(A) Unmodeled behaviors (B) Exactly modeled behaviors (C)

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 53 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

SC-DURING

New way to express concurrency in the platform Allows parallel execution of loosely-timed systems Exposes more bugs ( faithfulness Vs correction) Next steps (skipped from this talk):

◮ Worker threads Vs platform partitioning: DistemC ◮ Exploit FIFO-based communication: FOFIFON ◮ Integration in the design-flow: HLS code wrapping Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 54 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

This section

4

Extra-Functional Properties in TLM Time and Parallelism Power and Temperature Estimation

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 54 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Power and Temperature Estimation

An example

“How to validate embedded software that regulates the chip’s temperature?”

while (true) { // Temperature of one or more // locations of the chip read_sensors(); compute(); // Reduce frequency/voltage, // emergency stop, ... control_actuators(); }

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 55 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Power and Temperature Estimation

What precision? What applications?

control_actuators() read_sensors()

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 56 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Power and Temperature Estimation

What precision? What applications?

control_actuators() read_sensors()

TLM

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 56 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Power and Temperature Estimation

What precision? What applications?

control_actuators() read_sensors()

TLM

Arbitrary Temperature

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 56 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Power and Temperature Estimation

What precision? What applications?

control_actuators() read_sensors()

TLM

Scenario

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 56 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Power and Temperature Estimation

What precision? What applications?

control_actuators() read_sensors()

TLM

Computation on a model

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 56 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Power and Temperature Estimation

What precision? What applications?

control_actuators() read_sensors()

TLM

Computation on a model

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 56 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Power Consumption, Temperature, Heat Dissipation

Component Power (Joule effect) Dissipation (to environment) Dissipation (to another component) Dissipation (from another component)

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 57 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Power Consumption, Temperature, Heat Dissipation

Component Power (Joule effect) Dissipation (to environment) Dissipation (to another component) Dissipation (from another component) differential equations, solved by dedicated solvers

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 57 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Estimation with Power-State Models

// SystemC Process void compute() { while (true) { f(); wait(10); wait(); } }

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 58 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Estimation with Power-State Models

Sleep Idle Run 0 watt 0.1 watt 0.4 watt // SystemC Process void compute() { while (true) { set_state("run"); f(); wait(10); set_state("idle"); wait(); } }

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 58 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

From States to Consumption

State sleep run idle run Consumption 0 watt 0.4 watt 0.1 watt 0.4 watt Energy

(Consumption × Time) Total 2.5 Joules

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 59 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

From Power to Temperature

State sleep run idle run Consumption 0 watt 0.4 watt 0.1 watt 0.4 watt Temperature 20oC 40oC

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 60 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Traffic Models

TLM Bus CPU process = C++ code ITC Data RAM Instruction RAM GPIO VGA Timer Consumption = f(bits transmitted) Consumption = f ′(bits processed)

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 61 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Traffic Model and Loosely Timed Models

Real System

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 62 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Traffic Model and Loosely Timed Models

Real System f(); wait(40); g(); wait(35); Loosely-Timed Model

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 62 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Traffic Model and Loosely Timed Models

Real System f(); wait(40); g(); wait(35); Loosely-Timed Model Energy +3 +6 total=9

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 62 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Traffic Model and Loosely Timed Models

Real System f(); wait(40); g(); wait(35); Loosely-Timed Model Energy +3 +6 total=9 Temperature

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 62 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Traffic Model and Loosely Timed Models

Real System f(); wait(40); g(); wait(35); Loosely-Timed Model Energy +3 +6 total=9 Temperature Unrealistic peaks

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 62 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Traffic Model and Loosely Timed Models

Real System f(); wait(40); g(); wait(35); Loosely-Timed Model Frequency

3 40 trans/sec 6 35 trans/sec

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 62 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Traffic Model and Loosely Timed Models

Real System f(); wait(40); g(); wait(35); Loosely-Timed Model Frequency

3 40 trans/sec 6 35 trans/sec

Energy total=9

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 62 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Traffic Model and Loosely Timed Models

Real System f(); wait(40); g(); wait(35); Loosely-Timed Model Frequency

3 40 trans/sec 6 35 trans/sec

Energy total=9 Temperature

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 62 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Cosimulation SystemC and Extra-Functional Solver

SystemC Power/Temperature Solver States Temperature Functionality can depend on extra-functional data (e.g.: temperature sensor)

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 63 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Cosimulation of SystemC and Extra-Functional Solver

SystemC

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 64 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Cosimulation of SystemC and Extra-Functional Solver

SystemC Simulation Instant (Zero-time) Simulation Interval

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 64 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Cosimulation of SystemC and Extra-Functional Solver

SystemC Function Simulation Instant t = 0 Simulation Interval t ∈]0, 3[ Fonction Simulation Instant t = 3

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 64 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Cosimulation of SystemC and Extra-Functional Solver

SystemC P/To Function P/To Fonction ...

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 64 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Cosimulation of SystemC and Extra-Functional Solver

SystemC P/To Function P/To Fonction ... 1 1 SystemC runs simulation up to end of instant t

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 64 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Cosimulation of SystemC and Extra-Functional Solver

SystemC P/To Function P/To Fonction ... 1 2 1 SystemC runs simulation up to end of instant t 2 SystemC sends a request for extra-functional simulation on [t, t + d]

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 64 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Cosimulation of SystemC and Extra-Functional Solver

SystemC P/To Function P/To Fonction ... 1 2 3 1 SystemC runs simulation up to end of instant t 2 SystemC sends a request for extra-functional simulation on [t, t + d] 3 Extra-functional solver does the computation on the interval

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 64 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Cosimulation of SystemC and Extra-Functional Solver

SystemC P/To Function P/To Fonction ... 1 2 3 4 1 SystemC runs simulation up to end of instant t 2 SystemC sends a request for extra-functional simulation on [t, t + d] 3 Extra-functional solver does the computation on the interval 4 SystemC resumes simulation at beginning of instant t + d

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 64 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Extra-Functional Events

SystemC P/To End of instant 1 1 SystemC runs simulation until end of instant t

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 65 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Extra-Functional Events

SystemC P/To End of instant 1 Next instant 1 SystemC runs simulation until end of instant t 2 SystemC requests a extra-functional simulation in [t, t + d] or until “too hot”

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 65 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Extra-Functional Events

SystemC P/To End of instant 1 2 3 Too hot! 1 SystemC runs simulation until end of instant t 2 SystemC requests a extra-functional simulation in [t, t + d] or until “too hot” 3 Extra-functional runs simulation, encounters stop condition

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 65 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Extra-Functional Events

SystemC P/To End of instant 1 2 3 Too hot! 4 Fire IT 1 SystemC runs simulation until end of instant t 2 SystemC requests a extra-functional simulation in [t, t + d] or until “too hot” 3 Extra-functional runs simulation, encounters stop condition 4 SystemC resumes earlier than expected with interrupt.

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 65 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Extra-Functional Events

SystemC P/To End of instant 1 2 3 Too hot! 4 Fire IT ... 1 SystemC runs simulation until end of instant t 2 SystemC requests a extra-functional simulation in [t, t + d] or until “too hot” 3 Extra-functional runs simulation, encounters stop condition 4 SystemC resumes earlier than expected with interrupt.

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 65 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Results

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 66 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Outline

1

Introduction: Systems-on-a-Chip, Transaction-Level Modeling

2

Compilation of SystemC/TLM

3

Verification of SystemC/TLM

4

Extra-Functional Properties in TLM

5

Conclusion

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 66 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Conclusion

Transaction-Level Models of Systems-on-a-Chip Can they be Fast, Correct and Faithful?

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 67 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Conclusion

Fast

◮ Optimized compiler ◮ Parallelization techniques ◮ High abstraction level (Loose Timing)

Correct

◮ Formal verification

Faithful

◮ More ways to express concurrency ◮ Preserve Faithfulness of Temperature Models for Loose Timing Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 68 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

The new CASH Team, LIP (ENS-Lyon)

Compilation and Analysis for Software and Hardware

Sequential Program Parallel Program HPC Applications Parallelism Extraction Intermediate Parallel Representation Code Generation Hardware (FPGA) Software (CPU & accelerators) Optimization Dataflow Semantics Analysis Abstract Interpretation Simulation Polyhedral Model

Christophe Alias, Laure Gonnord, Matthieu Moy

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 69 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Questions?

Matthieu Moy (LIP) Transaction-Level Models of SoCs February 2018 < 70 / 70 >

SoCs and TLM Compilation Verification Extra-functional Conclusion

Sources

http://en.wikipedia.org/wiki/File:Diopsis.jpg (Peter John Bishop, CC Attribution-Share Alike 3.0 Unported) http://www.fotopedia.com/items/flickr-367843750 (oskay@fotopedia, CC Attribution 2.0 Generic)

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