Untethering the Rocket-Chip Producing a stand-alone lowRISC SoC Wei - - PowerPoint PPT Presentation

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Untethering the Rocket-Chip Producing a stand-alone lowRISC SoC Wei - - PowerPoint PPT Presentation

Mar 26, 2023 30 likes •122 views

Untethering the Rocket-Chip Producing a stand-alone lowRISC SoC Wei Song 07/10/2015 1 Background Rocket-chip An open-source SoC from UC Berkeley Rocket core RISC-V 64 ISA 5/6 stage single-issue in-order processor

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SLIDE 1

Untethering the Rocket-Chip

Producing a stand-alone lowRISC SoC

Wei Song 07/10/2015

1

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SLIDE 2

Background

  • Rocket-chip

– An open-source SoC from UC Berkeley – Rocket core

  • RISC-V 64 ISA
  • 5/6 stage single-issue in-order processor
  • Non-blocking L1 D$
  • Performance comparable to ARM Cortex-A5
  • Chisel (RTL, OO, functional)
  • Zynq FPGA (ARM A9), Linux bootable
  • Full cross-compilation tool chain

2

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SLIDE 3

Rocket-Chip

Rocket Core L2 & Coherence Manager L2 & Coherence Manager I$ D$

Rocket Tile

L2 & Coherence Manager Rocket Core I$ D$

Rocket Tile

Rocket Core I$ D$

Rocket Tile

Arbiter

Memory Controller

Host Interface TileLink/AXI AXI/MemIO AXI Bus ARM

UART SD EtherNet

Cached TileLink Uncached TileLink AXI MemIO L2 Bus

Issues:

  • 1. Must work with a companion core (ARM).
  • 2. No direct IO (peripheral) support.
  • 3. No direct bootloading.

3

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SLIDE 4

lowRISC-Chip

Rocket Core L2 & Coherence Manager L2 & Coherence Manager I$ D$

Rocket Tile

L2 & Coherence Manager Rocket Core I$ D$

Rocket Tile

Rocket Core I$ D$

Rocket Tile

Arbiter

Memory Controller

TileLink/AXI AXI Bus Cached TileLink Uncached TileLink AXI L2 Cache Bus Tag Cache

On-FPGA Boot Ram

L2 IO Bus AXI-Lite UART SD TileLink/AXI-Lite DMA DMA

coherent incoherent

Boot Minion Chisel SystemVerilog Uncached TileLink for MMIO

4

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SLIDE 5

Memory Mapped IO (1)

data meta mshrs mshr data meta dtlb Arbiter Arbiter

mshrs.replay

Arbiter

s1_req

s1_req.addr

= = = =

s1_tag_eq_way s1_addr read read resp resp

s2_req

amoalu

s2_hit write write

mshrs.request mshrs.meta_write

mem.req mem.grant cpu.req Stage 1 Stage 2 Stage 3 Stage 4

vpn ppn

rhs lhs

  • ut

s1_data s2_data s2_hit

cpu.resp Arb

s1_addr

EX MEM WB

5

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SLIDE 6

Memory Mapped IO (2)

data meta mshrs mshr data meta dtlb Arbiter Arbiter

mshrs.replay

Arbiter

s1_req

s1_req.addr

= = = =

s1_tag_eq_way s1_addr read read resp resp

s2_req

amoalu

write write

mshrs.request mshrs.meta_write

io.req io.grant cpu.req Stage 1 Stage 2 Stage 3 Stage 4

vpn ppn

rhs lhs

  • ut

s1_data s2_data s2_hit

cpu.resp Arb

s1_addr

ioaddr

s2_req.addr addr io

iomshr

request iomshr.replay io_data s1_io_data s2_io_data

s2_io_replay

io_data replay

mem.req mem.grant

6

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SLIDE 7

Bootloading Procedure (1)

Rocket Core L2 & Coherence Manager L2 & Coherence Manager I$ D$

Rocket Tile

L2 & Coherence Manager Rocket Core I$ D$

Rocket Tile

Rocket Core I$ D$

Rocket Tile

Arbiter

Memory Controller

TileLink/AXI AXI Bus L2 Cache Bus Tag Cache

On-FPGA Boot Ram

L2 IO Bus UART SD TileLink/AXI-Lite DMA DMA

coherent incoherent

Boot Minion Chisel SystemVerilog Uncached TileLink for MMIO

Bootloader Linux image

0x00000000 0x40000000 0x80000000

Memory: 0x00000000 – 0x3FFFFFFF IO space: 0x40000000 – 0xFFFFFFFF DDR3 memory in IO space (bypass L1/L2) Copy Linux image from SD to DDR3 using IO space (bypassing L1/L2).

7

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SLIDE 8

Bootloading Procedure (2)

Rocket Core L2 & Coherence Manager L2 & Coherence Manager I$ D$

Rocket Tile

L2 & Coherence Manager Rocket Core I$ D$

Rocket Tile

Rocket Core I$ D$

Rocket Tile

Arbiter

Memory Controller

TileLink/AXI AXI Bus L2 Cache Bus Tag Cache

On-FPGA Boot Ram

L2 IO Bus UART SD TileLink/AXI-Lite DMA DMA

coherent incoherent

Boot Minion Chisel SystemVerilog Uncached TileLink for MMIO

Bootloader Linux image

0x00000000 0x40000000 0x80000000

Memory: 0x40000000 – 0x7FFFFFFF -> 0x00000000 – 0x3FFFFFFF IO space: 0x80000000 – 0xFFFFFFFF DDR3 memory in memory space Linux image Remap DDR3 to Memory 0x00000000 – 0x3FFFFFFF Reset L1/L2 (clean any instructions from bootlaoder) All must be coded in one cache line (16 insns)

8

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SLIDE 9

Bootloading Procedure (3)

Rocket Core L2 & Coherence Manager L2 & Coherence Manager I$ D$

Rocket Tile

L2 & Coherence Manager Rocket Core I$ D$

Rocket Tile

Rocket Core I$ D$

Rocket Tile

Arbiter

Memory Controller

TileLink/AXI AXI Bus L2 Cache Bus Tag Cache

On-FPGA Boot Ram

L2 IO Bus UART SD TileLink/AXI-Lite DMA DMA

coherent incoherent

Boot Minion Chisel SystemVerilog Uncached TileLink for MMIO

Bootloader Linux image

0x00000000 0x40000000 0x80000000

Memory: 0x40000000 – 0x7FFFFFFF -> 0x00000000 – 0x3FFFFFFF IO space: 0x80000000 – 0xFFFFFFFF DDR3 memory in memory space Linux image

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