A UTOMATIC GENERATION OF DATAFLOW - BASED LOW - POWER E - PowerPoint PPT Presentation

Tiziana Fanni University of Cagliari A UTOMATIC GENERATION OF DATAFLOW - BASED LOW - POWER E RECONFIGURABLE SYSTEMS O L A B CPS D ESIGN F ROM CONCEPT TO IMPLEMENTATION

Cyber Physical Systems CGR approach for high run-time adaptivity Complex systems with different interacting components , that need to adapt their behavioural modality according to functional and non- functional requirements. http://www.cerbero-h2020.eu/

Cyber Physical Systems CGR approach for high run-time adaptivity Complex systems with different interacting components , that need to adapt their behavioural modality according to functional and non- functional requirements. Adopting Corse Grain Reconfigurable Approach to achieve high run-time adaptivity. http://www.cerbero-h2020.eu/

M ULTI D ATAFLOW C OMPOSER T OOL Coarse-Graine Reconfiguration Multi Dataflow Co-Processor Generator Composer Tool Structural Profiler Power Manager MDC design suite http://sites.unica.it/rpct/ 3/19

M ULTI D ATAFLOW C OMPOSER T OOL Coarse-Graine Reconfiguration Dataflow Specifications α .xdf β .xdf Multi Dataflow Co-Processor Generator Composer Tool γ .xdf Structural Profiler Power Manager MDC design suite http://sites.unica.it/rpct/ 3/19

M ULTI D ATAFLOW C OMPOSER T OOL Coarse-Graine Reconfiguration Dataflow Specifications α .xdf β .xdf Multi Dataflow Co-Processor Generator Composer Tool γ .xdf Structural Profiler N:1 Coarse Grained Reconfigurable Platform Power Manager LUT ID net B in1 α MDC design suite SB0 A SB1 out1 http://sites.unica.it/rpct/ SB2 C in3 γ F G 3/19 in2 β D E

M ULTI D ATAFLOW C OMPOSER T OOL Additional features Multi Dataflow Co-Processor Generator Composer Tool Structural Profiler Power Manager MDC design suite http://sites.unica.it/rpct/ 4/19

M ULTI D ATAFLOW C OMPOSER T OOL Additional features Structural Profiler: low-level feedback (from synthesis) and DSE for topology optimization. Multi Dataflow Co-Processor • (ASIC + FPGA) Generator Composer Tool Structural Profiler Co-Processor Generator : generation of ready-to-use Xilinx Ips • ( FPGA) Power Manager Power Manager : MDC design suite automatic application of clock-gating http://sites.unica.it/rpct/ and/or power-gating. • CG (ASIC + FPGA) 4/19 • PG(ASIC)

M ULTI D ATAFLOW C OMPOSER T OOL Additional features Structural Profiler: low-level feedback (from synthesis) and DSE for topology optimization. Multi Dataflow Co-Processor • (ASIC + FPGA) Generator Composer Tool Structural Profiler Co-Processor Generator : generation of ready-to-use Xilinx Ips • ( FPGA) Power Manager Power Manager : MDC design suite automatic application of clock-gating http://sites.unica.it/rpct/ and/or power-gating. • CG (ASIC + FPGA) 4/19 • PG(ASIC)

M ULTI D ATAFLOW C OMPOSER T OOL Power Management Coarse Grained Reconfigurable Platform LUT ID net B in1 α SB0 A SB1 out1 Multi Dataflow Co-Processor SB2 C Generator in3 γ Composer Tool F G Structural Profiler in2 β D E Power Manager Power Manager : MDC design suite automatic application of clock-gating http://sites.unica.it/rpct/ and/or power-gating. • CG (ASIC + FPGA) 5/19 • PG (ASIC)

M ULTI D ATAFLOW C OMPOSER T OOL Power Management Coarse Grained Reconfigurable Platform LUT ID net α B in1 α SB0 A SB1 out1 Multi Dataflow Co-Processor SB2 C Generator in3 γ Composer Tool F G Structural Profiler in2 β D E Power Manager Power Manager : MDC design suite automatic application of clock-gating http://sites.unica.it/rpct/ and/or power-gating. • CG (ASIC + FPGA) 5/19 • PG (ASIC)

M ULTI D ATAFLOW C OMPOSER T OOL Power Management Coarse Grained Reconfigurable Platform LUT ID net α B in1 α SB0 A SB1 out1 Multi Dataflow Co-Processor SB2 C Generator in3 γ Composer Tool F G Structural Profiler β in2 β D E Power Manager Power Manager : MDC design suite automatic application of clock-gating http://sites.unica.it/rpct/ and/or power-gating. • CG (ASIC + FPGA) 5/19 • PG (ASIC)

M ULTI D ATAFLOW C OMPOSER T OOL Power Management Coarse Grained Reconfigurable Platform LUT ID net α B in1 α SB0 A SB1 out1 Multi Dataflow γ Co-Processor SB2 C Generator in3 γ Composer Tool F G Structural Profiler β in2 β D E Power Manager Power Manager : MDC design suite automatic application of clock-gating http://sites.unica.it/rpct/ and/or power-gating. • CG (ASIC + FPGA) 5/19 • PG (ASIC)

M ULTI D ATAFLOW C OMPOSER T OOL Power Management Coarse Grained Reconfigurable Platform LUT ID net α LR1 α γ LR4 B in1 α α SB0 γ A SB1 β α LR2 γ out1 Multi Dataflow γ Co-Processor LR4 SB2 C Generator in3 γ Composer Tool F G γ LR5 Structural Profiler β in2 β D E Power Manager β LR3 Power Manager : MDC design suite automatic application of clock-gating http://sites.unica.it/rpct/ and/or power-gating. • CG (ASIC + FPGA) 5/19 • PG (ASIC)

Acknowledgements The CERBERO project has received funding from the EU Commission’s H2020 Programme under grant agreement No 732105.