Abdullah Baz, Delong Shang, Fei Xia and Alex Yakovlev - - PowerPoint PPT Presentation

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Aug 24, 2022 393 likes •786 views

Abdullah Baz, Delong Shang, Fei Xia and Alex Yakovlev Microelectronic System Design Group, School of EECE, Newcastle University Agenda Introduction Research motivation Methodology Proposed solution Analysis and Results

SLIDE 1

Abdullah Baz, Delong Shang, Fei Xia and Alex Yakovlev Microelectronic System Design Group, School of EECE, Newcastle University

SLIDE 2

Agenda

Introduction Research motivation Methodology Proposed solution Analysis and Results Conclusion Future work

SLIDE 3

Introduction

Pass transistors

SLIDE 4

SRAM operation

Reading:

Precharge bitlines Open WL one bitline will be discharged

Writing:

Precharge bitlines Enable write driver pull down one of the bitline Open WL new data will be written

SLIDE 5

SRAM timing

SRAM works based on timing assumptions to ensure safe

reading and correct writing

The timing control block controls the time for

precharging, opening the WL, enabling the write driver

Timing control methods:

Clock Delay line (inverters chain) Replica bitline (dummy column)

SLIDE 6

Previous work

SI for reading and delay line for writing [A four phase handshaking

asynchronous static RAM design for selftimed systems by Vincent Wing-Yun Sit et al.]

SI for reading and delay line for writing based on timing

assumption (vdd ranges from 0.7V to 1.5V) [GHz asynchronous SRAM in

65nm by J. Dama and A. Lines]

New cell with 13T [Design and verification of a self-timed RAM by L.S. Nielsen and J. Staunstrup]

SLIDE 7

Previous work (SI reading)

SLIDE 8

Previous work

SI for reading and delay line for writing [A four phase handshaking

asynchronous static RAM design for selftimed systems by Vincent Wing-Yun Sit et al.]

SI for reading and delay line for writing based on timing

assumption (vdd ranges from 0.7V to 1.5V) [GHz asynchronous SRAM in

65nm by J. Dama and A. Lines]

New cell with 13T [Design and verification of a self-timed RAM by L.S. Nielsen and J. Staunstrup]

SLIDE 9

Behaviour of SRAM under variable Vdd

Investigate the latency mismatch between the SRAM and

the inverter-chain under different Vdds

SLIDE 10

Investigation results

SLIDE 11

SRAM timing variations

The timing variations of SRAM can be caused by:

Nondeterministic supply voltage (energy harvesting) Process Voltage Temperature (PVT) variations

Effect of timing variations:

Read failure: open WL before deactivation precharge Access failure: close WL before discharge one of the

bitlines

Write failure: close WL before data is written

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Methodology

Asynchronous design regulates the data flow of the circuit

based on the actual speed of the circuit

The handshaking protocol tracks any latency variations Self-timed design with completion detection can adapt

with Vdds

SLIDE 13

Our contribution

Prove that typical delay line can not track (without

penalty) SRAM timing variation under highly variable supply voltage

Design a novel asynchronous fully SI SRAM memory

based on the 6T cell (no need to increase number of the transistor or change the architecture)

Demonstrate the ability of our memory to work under

wide range of variable supply voltage

Propose new method to build delay elements for bundled

SRAM memory

SLIDE 14

Proposed solution

1 Kbit (64x16) fully SI SRAM (6T)

SLIDE 36

Conclusion

Under non-deterministic supply voltage, the first concern

is the timing variations

Typical delay line is not suitable to track the timing

variations in SRAM

Asynchronous design can solve this problem at the

expense of area and energy

SLIDE 37

Future work

Find out an accurate model for the harvester to test our

proposed SRAM

Find out the overhead of the proposed solution in terms of

area and performance

Analyze the proposed controller under the process

variations

Fabricate the design to demonstrate its functionally

SLIDE 38