Development of TRBv3 & FIRST Results of FIRST Test Beam Cahit - - PowerPoint PPT Presentation

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Development of TRBv3 & FIRST Results of FIRST Test Beam Cahit - - PowerPoint PPT Presentation

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Development of TRBv3 & FIRST Results of FIRST Test Beam Cahit Uur Helmholtz-Institut Mainz XL. PANDA Collaboration Meeting 5 March 2012, GSI Darmstadt, Germany 05.03.2012 | Cahit Uur | XL. PANDA Collaboration Meeting Outline

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05.03.2012 | Cahit Uğur | XL. PANDA Collaboration Meeting

Development of TRBv3 & FIRST Results of FIRST Test Beam

Cahit Uğur

Helmholtz-Institut Mainz

  • XL. PANDA Collaboration Meeting

5 March 2012, GSI Darmstadt, Germany

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SLIDE 2

05.03.2012 | Cahit Uğur | XL. PANDA Collaboration Meeting

Outline

  • Motivation
  • TDC in FPGA
  • Laboratory test results
  • DIRC Prototype test beam setup and first results
  • Conclusion & Outlook
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SLIDE 3

05.03.2012 | Cahit Uğur | XL. PANDA Collaboration Meeting

Motivation

  • to have high resolution, high channel

density, low cost

  • to replace ASIC-HPTDCs from CERN
  • to provide solutions for different

requirements e.g. higher resolution, zero dead time

  • to provide different measurement

capabilities, e.g. ToF, Charge

  • to use in different detectors for different

experiments

TDC Readout Board v2

Photo by Gaby Otto, GSI Darmstadt, 22.12.2006.

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SLIDE 4

05.03.2012 | Cahit Uğur | XL. PANDA Collaboration Meeting

Motivation

TDC Readout Board v3

Photo by Gaby Otto, GSI Darmstadt, 22.12.2006.

  • to have high resolution, high channel

density, low cost

  • to replace ASIC-HPTDCs from CERN
  • to provide solutions for different

requirements e.g. higher resolution, zero dead time

  • to provide different measurement

capabilities, e.g. ToF, Charge

  • to use in different detectors for different

experiments

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SLIDE 5

05.03.2012 | Cahit Uğur | XL. PANDA Collaboration Meeting

TDC in FPGA

Tapped Delay Line Method

  • Tapped delay line is used for fine

time measurements – suits well with the FPGA architecture

  • Delay elements are realised by LUTs
  • Fast carry chain structure forms the

delay line

  • Registers are used to sample the

delay line

Tapped Delay Line Method [1] PFU Diagramm [2]

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SLIDE 6

05.03.2012 | Cahit Uğur | XL. PANDA Collaboration Meeting

TDC in FPGA

Architecture of the TDC

Slice diagram with LUTs programmed as Full Adders Delay line is realised with Full Adders [3] TDC Architecture

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SLIDE 7

05.03.2012 | Cahit Uğur | XL. PANDA Collaboration Meeting

Laboratory Test Results

Time resolution test Mean measurement test

  • Time difference measured between 2

channels

  • Δt = (tcoarse1- tcoarse2) - (tfine1- tfine2)
  • RMS measured: 10.34 ps against the

same clock

  • Resolution: 10.34 ps / √2 = 7.3 ps RMS

Time difference between two measurements

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SLIDE 8

05.03.2012 | Cahit Uğur | XL. PANDA Collaboration Meeting

DIRC Prototype Test Beam @ MAMI

25 February 2012

Electron beam Beam energy: 855 MeV Beam spread: 0,3o

TRB3 & Readout Electronics Triggerless! Discriminator MCP & Pre-amplifier Scintillator Quarz bar

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SLIDE 9

05.03.2012 | Cahit Uğur | XL. PANDA Collaboration Meeting

FIRST Results from the FIRST Beam

Time Correlation between pixel 45 & 55

Oscilloscope result

PRELIMINARY PRELIMINARY

TDC result

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SLIDE 10

05.03.2012 | Cahit Uğur | XL. PANDA Collaboration Meeting

Measured time difference between the pixel 45 and scintillator Oscilloscope result TDC result

Counts

PRELIMINARY PRELIMINARY

FIRST Results from the FIRST Beam

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SLIDE 11

05.03.2012 | Cahit Uğur | XL. PANDA Collaboration Meeting

FIRST Results from the FIRST Beam

Bin width comparison of Beam results and Lab results

PRELIMINARY PRELIMINARY

Beam result Lab result

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SLIDE 12

05.03.2012 | Cahit Uğur | XL. PANDA Collaboration Meeting

Conclusion & Outlook

  • Multi-Purpose TDC in FPGA chip has been developed
  • The first board has been tested with real beam for the FIRST time!
  • For test purposes 6 channels were used
  • Time data was taken successfully with the electronics prototype
  • Time distribution and correlation information of the pixels are consistent with the
  • scilloscope
  • For more tests the TDC will be tested in the next Hades beam time during April

and DIRC prototype beam time in May

  • More time information will be collected (rising and falling edges – ToT – of the

signals)

  • More channels will be implemented
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SLIDE 13

05.03.2012 | Cahit Uğur | XL. PANDA Collaboration Meeting

References

[1] J. Kalisz, Review of methods for time interval measurements with picosecond resolution, Metrologia, 2004. [2] LatticeECP2/M Family Handbook, HB1003, Version 04.3, March 2009. [3] J. Song et al., A high-resolution time-to-digital converter implemented in field- programmable-gate-arrays,IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2006.

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05.03.2012 | Cahit Uğur | XL. PANDA Collaboration Meeting

Backup Slides

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SLIDE 15

05.03.2012 | Cahit Uğur | XL. PANDA Collaboration Meeting

Architecture of Time-to-Digital Converter

[4] Lattice ECP2M FPGA Slice Diagram, PFU Diagram and Floorplan

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SLIDE 16

05.03.2012 | Cahit Uğur | XL. PANDA Collaboration Meeting

Architectural Effects of FPGA

  • Effect of primary clock line in

the FPGA

  • Effect of longer inter-slice

routings

  • Effect of PFU architecture
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SLIDE 17

05.03.2012 | Cahit Uğur | XL. PANDA Collaboration Meeting

Architectural Effects of FPGA

  • Effect of primary clock line in

the FPGA

  • Effect of longer inter-slice

routings

  • Effect of PFU architecture
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SLIDE 18

05.03.2012 | Cahit Uğur | XL. PANDA Collaboration Meeting

Architectural Effects of FPGA

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SLIDE 19

05.03.2012 | Cahit Uğur | XL. PANDA Collaboration Meeting

Architectural Effects of FPGA

  • Effect of primary clock line in

the FPGA

  • Effect of longer inter-slice

routings

  • Effect of PFU architecture
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SLIDE 20

05.03.2012 | Cahit Uğur | XL. PANDA Collaboration Meeting

Wave Union Launcher

  • More than one delay line is necessary

in order to reduce the effect of wide bins

  • Wave union launcher is implemented
  • Bin widths & non-linearities are

reduced

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SLIDE 21

05.03.2012 | Cahit Uğur | XL. PANDA Collaboration Meeting

  • More virtual bins
  • Narrower bins
  • Homogeneous bin

distribution

Wave Union Launcher

Bins: ~240 Mean: ~20 ps Max: ~45 ps Bins: ~520 Mean: ~10 ps Max: ~35 ps

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SLIDE 22

05.03.2012 | Cahit Uğur | XL. PANDA Collaboration Meeting

Statistical Error & Resolution

  • Time difference measured between 2

channels

  • Δt = (tcoarse1- tcoarse2) - (tfine1- tfine2)
  • RMS measured: 10.34 ps

against same clock

  • Resolution: 10.34 ps / √2 = 7.3 ps
  • Effect of 2 transitions:

14.82 ps / 10.34 ps = 1.43 factor

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SLIDE 23

05.03.2012 | Cahit Uğur | XL. PANDA Collaboration Meeting

Fine Time Correlation

Beam result Lab result