Bias-Stress Instability in GaN Field-Effect Transistors Jess A. del - - PowerPoint PPT Presentation

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Bias-Stress Instability in GaN Field-Effect Transistors Jess A. del - - PowerPoint PPT Presentation

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Bias-Stress Instability in GaN Field-Effect Transistors Jess A. del Alamo and Alex Guo Microsystems Technology Laboratories Massachusetts Institute of Technology MRS Spring Meeting Phoenix, AZ, April 2-6, 2018 Acknowledgements: S.

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SLIDE 1

Bias-Stress Instability in GaN Field-Effect Transistors

Jesús A. del Alamo and Alex Guo

Microsystems Technology Laboratories

Massachusetts Institute of Technology

Acknowledgements:

  • S. Warnock (MIT Lincoln Lab.), J. Franco (IMEC)
  • Sponsors: MIT-MTL GaN Energy Initiative, NDSEG Fellowship

MRS Spring Meeting

Phoenix, AZ, April 2-6, 2018

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Important role for GaN power electronics in future

Application space for future power electronics

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SLIDE 3

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Favored structure: GaN MIS-HEMT

  • High-mobility 2DEG at AlGaN/GaN interface
  • Dielectric to suppress gate leakage current and increase gate swing
  • On Si for low cost
  • MIS-HEMT: Metal-Insulator-Semiconductor High Electron

Mobility Transistor 2DEG

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SLIDE 4
  • Si substrate  defects in GaN
  • Multiple interfaces, many trapping sites
  • Uncertain electric field distribution across gate stack

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Main concern with GaN MIS-HEMTs: reliability and stability

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SLIDE 5

5

Bias-Temperature Instability (BTI)

Device stability during operation: key concern, particularly VT

Al2O3/AlGaN/GaN Lagger, IEDM 2012 SiN/AlGaN/GaN Zhang, SST 2014 Winzer, PSSa 2016 HfO2/AlGaN/GaN

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SLIDE 6

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BTI in GaN MOSFETs

Simpler than MIS-HEMTs: single GaN/oxide interface

  • Industrial prototype devices
  • Gate dielectric: SiO2/Al2O3 (EOT=40 nm)

Guo, IRPS 2015 Guo, IRPS 2016 Guo, TED 2017

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SLIDE 7

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Experimental methodology

1. Device initialization through thermal detrapping step

Minor impact: ΔVT < 20 mV, ΔS < 30 mV/dec

2. Stress and characterization: measure VT, peak gm, S at VDS=0.1 V

After 50 characterization runs: ΔVT < 10 mV, Δgm < 0.02 mS/mm, ΔS < 15 mV/dec

3. Recovery phase with terminals grounded and periodic characterization 4. Final thermal detrapping Guo, TED 2017

Constant-VGS, stress-interrupt experiments at RT:

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Threshold voltage evolution

  • PBTI: VGS,stress>0  ΔVT>0
  • NBTI: VGS,stress<0  ΔVT<0
  • |ΔVT| increases with stress voltage and time
  • Fully recoverable  no defect generation

Guo, TED 2017

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SLIDE 9

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Transconductance evolution

Guo, TED 2017

  • PBTI: VGS,stress>0  gm,max↓
  • NBTI: VGS,stress<0  gm,max↑
  • |Δgm| increases with stress voltage and time
  • Fully recoverable  no defect generation
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10

Subthreshold swing evolution

Guo, TED 2017

  • PBTI: VGS,stress>0  S unchanged
  • NBTI: VGS,stress<0  S unchanged
  • No interface state generation
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SLIDE 11

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Correlation between ΔVT and Δgm

  • Good correlation between PBTI and NBTI during stress

and recovery

  • One physical mechanism, fully reversible

PBTI PBTI NBTI NBTI

Guo, TED 2017

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SLIDE 12

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Functional dependence of VT

Guo, TED 2017

VT well described by power-law function: Consistent with electron trapping/detrapping in oxide

PBTI NBTI PBTI NBTI

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PBTI/NBTI: Recoverable electron trapping/detrapping in oxide

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SLIDE 14

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PBTI/NBTI: Recoverable electron trapping/detrapping in oxide

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SLIDE 15

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PBTI/NBTI: Recoverable electron trapping/detrapping in oxide

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SLIDE 16

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PBTI/NBTI: Recoverable electron trapping/detrapping in oxide

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SLIDE 17

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PBTI/NBTI: Recoverable electron trapping/detrapping in oxide

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SLIDE 18

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PBTI in HfO2/InGaAs system

Cai, IEDM 2016

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SLIDE 19

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Oxide trapping in other high-k/MOS systems

Zafar, TDMR 2005 Al2O3/Si Al2O3/InGaAs HfO2/Si

Al2O3/InGaAs

Franco, IRPS 2014

Si HK/MG

HfO2/Ge Franco, IEDM 2017 Wu, IEDM 2005

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Oxide trapping in other high-k/MOS systems

Zafar, TDMR 2005 Al2O3/Si Al2O3/InGaAs HfO2/Si

Al2O3/InGaAs

Franco, IRPS 2014

Si HK/MG

HfO2/Ge Franco, IEDM 2017 Wu, IEDM 2005

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SLIDE 21

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Oxide trapping in other high-k/MOS systems

Zafar, TDMR 2005 Al2O3/Si Al2O3/InGaAs HfO2/Si

Al2O3/InGaAs

Franco, IRPS 2014

Si HK/MG

HfO2/Ge Franco, IEDM 2017 Wu, IEDM 2005

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SLIDE 22

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Oxide trapping in other high-k/MOS systems

Zafar, TDMR 2005 Al2O3/Si Al2O3/InGaAs HfO2/Si

Al2O3/InGaAs

Franco, IRPS 2014

Si HK/MG

HfO2/Ge Franco, IEDM 2017 Wu, IEDM 2005

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SLIDE 23

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Oxide trapping in other high-k/MOS systems

Zafar, TDMR 2005 Al2O3/Si Al2O3/InGaAs HfO2/Si

Al2O3/InGaAs

Franco, IRPS 2014

Si HK/MG

HfO2/Ge Franco, IEDM 2017 Wu, IEDM 2005

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What are these defects?

Liu, APL 2010 Formation energy of O vacancies:

Prime suspect: O vacancies

Al2O3/GaN band alignment:

Defect states in Al2O3 right above conduction band edge of GaN

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What are these defects?

Liu, APL 2010 Formation energy of O vacancies:

Prime suspect: O vacancies

Al2O3/GaN band alignment:

Defect states smear into bands in amorphous material

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How to mitigate? Look at CMOS literature

LaSiO interlayer

Franco, IRPS 2017

Short, high-T anneal

Franco, IRPS 2017

AC BTI more benign

Krishnan, IRPS 2012

Reduce IG

Krishnan, IRPS 2012

Reduce high-k thickness

Cartier, IEDM 2011

tIL↑

Introduce SiON interfacial layer Cartier, IEDM 2011

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SLIDE 27

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How to mitigate? Look at CMOS literature

LaSiO interlayer

Franco, IRPS 2017

Short, high-T anneal

Franco, IRPS 2017

AC BTI more benign

Krishnan, IRPS 2012

Reduce IG

Krishnan, IRPS 2012

Reduce high-k thickness

Cartier, IEDM 2011

tIL↑

Introduce SiON interfacial layer Cartier, IEDM 2011

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SLIDE 28

28

How to mitigate? Look at CMOS literature

LaSiO interlayer

Franco, IRPS 2017

Short, high-T anneal

Franco, IRPS 2017

AC BTI more benign

Krishnan, IRPS 2012

Reduce IG

Krishnan, IRPS 2012

Reduce high-k thickness

Cartier, IEDM 2011

tIL↑

Introduce SiON interfacial layer Cartier, IEDM 2011

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SLIDE 29

29

How to mitigate? Look at CMOS literature

LaSiO interlayer

Franco, IRPS 2017

Short, high-T anneal

Franco, IRPS 2017

AC BTI more benign

Krishnan, IRPS 2012

Reduce IG

Krishnan, IRPS 2012

Reduce high-k thickness

Cartier, IEDM 2011

tIL↑

Introduce SiON interfacial layer Cartier, IEDM 2011

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SLIDE 30

30

How to mitigate? Look at CMOS literature

LaSiO interlayer

Franco, IRPS 2017

Short, high-T anneal

Franco, IRPS 2017

AC BTI more benign

Krishnan, IRPS 2012

Reduce IG

Krishnan, IRPS 2012

Reduce high-k thickness

Cartier, IEDM 2011

tIL↑

Introduce SiON interfacial layer Cartier, IEDM 2011

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SLIDE 31

31

How to mitigate? Look at CMOS literature

LaSiO interlayer

Franco, IRPS 2017

Short, high-T anneal

Franco, IRPS 2017

AC BTI more benign

Krishnan, IRPS 2012

Reduce IG

Krishnan, IRPS 2012

Reduce high-k thickness

Cartier, IEDM 2011

tIL↑

Introduce SiON interfacial layer Cartier, IEDM 2011

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SLIDE 32

32

How to mitigate? Look at CMOS literature

LaSiO interlayer

Franco, IRPS 2017

Short, high-T anneal

Franco, IRPS 2017

AC BTI more benign

Krishnan, IRPS 2012

Reduce IG

Krishnan, IRPS 2012

Reduce high-k thickness

Cartier, IEDM 2011

tIL↑

Introduce SiON interfacial layer Cartier, IEDM 2011

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SLIDE 33

33

How to mitigate? Look at CMOS literature

LaSiO interlayer

Franco, IRPS 2017

Short, high-T anneal

Franco, IRPS 2017

AC BTI more benign

Krishnan, IRPS 2012

Reduce IG

Krishnan, IRPS 2012

Reduce high-k thickness

Cartier, IEDM 2011

tIL↑

Introduce SiON interfacial layer Cartier, IEDM 2011

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SLIDE 34
  • Three regimes: Negative ∆VT  positive ∆VT  negative ∆VT
  • Permanent negative ∆VT after final thermal detrapping

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NBTI under harsher stress

Guo, IRPS 2016

High-voltage and high-temperature stress:

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SLIDE 35
  • Three regimes: Negative ∆VT  positive ∆VT  negative ∆VT
  • Permanent negative ∆VT after final thermal detrapping

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NBTI under harsher stress

Guo, IRPS 2016

High-voltage and high-temperature stress:

Trapping in GaN channel under gate edge (recoverable)

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SLIDE 36
  • Three regimes: Negative ∆VT  positive ∆VT  negative ∆VT
  • Permanent negative ∆VT after final thermal detrapping

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NBTI under harsher stress

Guo, IRPS 2016

High-voltage and high-temperature stress:

Trapping in GaN channel under gate edge (recoverable) Interface trap formation (permanent)

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Conclusions

  • PBTI and NBTI (benign stress):

‒ recoverable ΔVT, Δgm due to electron trapping/detrapping in pre- existing oxide traps ‒ Experimental observations well described by oxide trapping model

  • Many avenues for mitigation  study Si high-k/MOS literature
  • New degradation physics under harsher stress (NBTI):

‒ recoverable ΔVT>0, ΔS due to electron trapping in substrate ‒ non-recoverable ΔVT<0, Δgm, ΔS due to interface state formation