Chair of Network Architectures and Services Department of Informatics Technical University of Munich
Evaluation of Online Schedule Synthesis Algorithms for Time-based - - PowerPoint PPT Presentation
Evaluation of Online Schedule Synthesis Algorithms for Time-based - - PowerPoint PPT Presentation
Chair of Network Architectures and Services Department of Informatics Technical University of Munich Evaluation of Online Schedule Synthesis Algorithms for Time-based Scheduled Time Sensitive Networks Intermediate talk for the Masters Thesis
Outline
- Introduction to Time Sensitive Networking
- Thesis Objectives
- Approach
- Network Calculus Model for WCD Analysis in TSN Networks
- Building a TSN emulation environment based on Mininet
- GCL Synthesis Algorithms
- Testbed Evaluations
- Further Steps and Future Outlook
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Introduction to Time Sensitive Networking
- Set of IEEE standards and additions to the IEEE 802.3 Ethernet standard, for providing
deterministic services and meet the requirements for bounded latency packet transmission
- n Layer 2
- IEEE Time Sensitive Networking Task Group, former Audio Video Bridging (AVB) Task
Group
- High interest on TSN in the following industry sectors:
- Factroy Automation (Industry 4.0)
- Automotive
- Aerospache/Avionic
- Autonomous Driving
- etc.
- The Standarization process is still ongoing, some important standards are not yet finished
and published
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Introduction to Time Sensitive Networking
IEEE TSN Standards
Figure 1: TSN components [2]
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Thesis Objectives
Problem Statement
- Currently the TSN standardization is lacking a proper way for dynamically (re-)configure
TSN-Networks
- The majority of the shown TSN-Demonstrations (e.g. on fairs) are statically configured and
- nly work with prior knowledge about the complete network
- The scheduling problem introduced by IEEE 802.1Qbv (Time-based Scheduling) can be-
come non-trival to solve for large Networks
- But: There have been recent research efforts, in order to tackle the dynamic Schedule
Synthesis Goal of this Thesis: Compare and evaluate different approaches for dynamic Schedule Synthe- sis for time-based scheduled TSN-Networks
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Thesis Objectives
- Objective 1:
Implement Network Calculus Model for determining Worst Case Delay (WCD) of flows in Time Sensitive Networks with static Schedule Configuration
- Objective 2:
Implement an emulation environment based on mininet for time-based scheduled TSN Networks
- Objective 3:
Implement, validate and optimize Schedule Synthesis Algorithms for time-based scheduled TSN Networks
- Objective 4:
Evaluation and comparison the different Synthesis Algoritms according to performance, execution time and validity of the generated Schedules
- Objective 5 (Optional):
Create a testbed/demonstrator utilizing the evaluated online mechnaisms for dynamic sched- ule generation and adaption on real TSN-capable Hardware
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Approach
IEEE 802.1Qbv - Time Aware Scheduler
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Gate Gate Gate Gate Gate Gate Gate Gate GCL T1 : 1000 0000 T2 : 0111 1111 T3 : 0111 1111 T4 : 0111 1111 T5 : 0111 1111 TGCL Transmission Selection
Figure 2: Time-based Scheduler (GCL: Gate Control List, TGCL : Cycle Time of the schedule)
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Approach
IEEE 802.1Qbv - Time Aware Scheduler
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Gate Gate Gate Gate Gate Gate Gate Gate GCL T1 : 1000 0000 T2 : 0111 1111 T3 : 0111 1111 T4 : 0111 1111 T5 : 0111 1111 TGCL Transmission Selection
Figure 3: Time-based Scheduler (GCL: Gate Control List, TGCL : Cycle Time of the schedule)
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Approach
Example TSN Network
ES1 ES2 ES3 ES4 SW1 SW2 Flow 1 Flow 2
GCL GCL GCL GCL GCL GCL
CUC CNC Figure 4: Template
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Approach
Network Calculus Model for WCD Analysis in TSN Networks
- L. Zaho et. al proposed in [4] a Network Calculus model for determining the Worst Case
Delay of flows in time-based scheduled TSN Networks
- Works on statically configured time-based scheduled TSN Networks (GCLs given)
- Inputs → network topology, GCLs, Flow information, Flow of Interest (FOI)
- Output → End-to-End WCD of the FOI
- Implemented Parameter Calculation for the resulting service curves (β) for each port on
the FOIs Path in Python
- A lot of work tended to be optimal preparation of the input data for calculation of Overlap-
ping scenarios (more on next slide)
- Opens:
- Feed parameters into DiscoDNC1 Framework for reliable WCD calculation
- Validate our implementation using the in [4] presented evaluation results
1 https://disco.cs.uni-kl.de/index.php/projects/disco-dnc
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Approach
Building a TSN emulation environment based on Mininet
- Nice to Have: A flexible Network Emulator that can do time-based scheduling according to
the standard
- Idea: Use recently added TAPRIO2 kernel net-scheduler module to add time-based sched-
uling capabilities to mininet3
- TAPRIO can be easily configured as any other Queuing Dicipline (qdisc) using the iproute2
tool tc (example next slide)
- Problem:
- mininet uses veth (virtual ethernet) interfaces
- veth interfaces implement no Transmit (TX) Queues
- TAPRIO requires TX Queues to work
- Opens:
- Adapt veth implementation to support multiple TX queues and thus supports TAPRIO
- Create a test framework on running automated evaluations for the Network Calculus Model and
the GCL Synthesis Algorithms on various netwrok topologies
2 http://man7.org/linux/man-pages/man8/tc-taprio.8.html 3 http://mininet.org/
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Approach
Overlapping Scenarios in GCLs
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Approach
GCL Synthesis Algorithms
- Two main Related Works on GCL Synthesis Algorithms:
- Algorithm 1: R. Oliver et. al proposed in [3] a GCL Synthesis algorithm based on Array Theory
Encoding (TA) for Satisfiability Modulo Theory (SMT)
- Algorithm 2: S. Craciunas et. al proposed in [1] a GCL Synthesis Algorithm based on Integer
Linear Programming (ILP) for SMT
- Some other interesting approaches: No-wait Packet Scheduling Problem (NW-PSP), sim-
ple heuristic approaches
- Opens:
- Implement and Evaluate Algorithm 1 and 2 using z34 SMT/OMT solver for Python
- Implement and Evaluate a simple heuristic schedule synthesis algorithm
4 https://github.com/Z3Prover/z3
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Approach
Testbed Evaluations
- Idea: Show off the functionality of a dynamically configurable time-based scheduled TSN
Network on real Hardware
- Most of the required software (sender, receiver, visualization/control tool) is already
implemented
- Once the GCL Synthesis Algorithms have been implemented, we can setup a demonstrator
- User can add/remove flows with certain properties to the TSN-Network and network will
automatically re-configure itself and shows off acheived end-to-end packet latencies for the FOI
- Open: Finish implementation and setup of the demonstrator, once all missing pieces are
done
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Further Steps and Future Outlook
Further Steps and Future Outlook
- Network Calculus Model implementation almost finished, first evaluation results expected
soon
- Facing some problems regarding enabling TAPRIO on mininet (How can we implement TX
Queues on veth interfaces ?)
- For the next major phase of this thesis, we will focus on the implementation, evaluation and
possible optimizations of the GCL Synthesis Algorithms
- If we have enough time, we will create a demonstrator, which shows the dynamic schedule
adaption using real TSN-capable Hardware Thanks for your Attention !
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Backup
TAPRIO configuration example tc qdisc add dev IFACE parent root handle 100 taprio num_tc 3 # Number of traffic Classes map 2 2 1 0 2 2 2 2 2 2 2 2 2 2 2 2 # Map Traffic Class -> SKB Priority queues 1@0 1@1 2@2 # Map Traffic Class -> HW Queue base-time 10000000 # Start Time sched-entry S 03 300000 # 1st Schedule Entry sched-entry S 02 300000 # 2nd Schedule Entry sched-entry S 06 400000 # 3rd Schedule Entry clockid CLOCK_TAI # Clock Source to use (Reference Clock)
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Bibliography
[1]
- S. S. Craciunas, R. S. Oliver, M. Chmelík, and W. Steiner.
Scheduling real-time communication in ieee 802.1qbv time sensitive networks. In Proceedings of the 24th International Conference on Real-Time Networks and Systems, RTNS ’16, pages 183–192, New York, NY, USA, 2016. ACM. [2]
- J. Farkas.
Introduction to IEEE 802.1 - Focus on the Time-Sensitive Networking Task Group, 2017. http://www.ieee802.org/1/files/public/docs2017/tsn-farkas-intro-0517-v01.pdf. [3]
- R. Serna Oliver, S. S. Craciunas, and W. Steiner.
Ieee 802.1qbv gate control list synthesis using array theory encoding. In 2018 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pages 13–24, April 2018. [4]
- L. Zhao, P
. Pop, and S. S. Craciunas. Worst-case latency analysis for ieee 802.1qbv time sensitive networks using network calculus. IEEE Access, 6:41803–41815, 2018.
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