Fast Multi-Precision Multiplication for Public-Key Cryptography on - - PowerPoint PPT Presentation

▶
fast multi precision multiplication for public key
SMART_READER_LITE
LIVE PREVIEW

Fast Multi-Precision Multiplication for Public-Key Cryptography on - - PowerPoint PPT Presentation

Dec 02, 2022 157 likes •476 views

Institute for Applied Information Processing and Communications (IAIK) Fast Multi-Precision Multiplication for Public-Key Cryptography on Embedded Microprocessors Michael Hutter and Erich Wenger CHES 2011 Institute for Applied Information

slide-1
SLIDE 1

Institute for Applied Information Processing and Communications (IAIK) 1

TU Graz/Computer Science/IAIK/VLSI/Name Project

1

TU Graz/Computer Science/IAIK/SEnSE CHES 2011 Nara, 01.10.2011

Fast Multi-Precision Multiplication for Public-Key Cryptography on Embedded Microprocessors

Michael Hutter and Erich Wenger

CHES 2011

Institute for Applied Information Processing and Communications (IAIK), Graz University of Technology

slide-2
SLIDE 2

Institute for Applied Information Processing and Communications (IAIK) 2

TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011

What is this talk about?

New multiplication technique:

Operand-Caching Multiplication

Idea: trade load against less store instructions by caching of operands Result: 10% improvement compared to related work on the ATmega128

slide-3
SLIDE 3

Institute for Applied Information Processing and Communications (IAIK) 3

TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011

Multi-Precision Multiplication

Most important operation in PKC Applied in modern processors (8, 16, 32, 64 bits) Optimizations

Reduce expensive operations Minimize number of load and/or store instructions

slide-4
SLIDE 4

Institute for Applied Information Processing and Communications (IAIK) 4

TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011

Operand Scanning

“Schoolbook method”

a * b = c

Row-wise processing 2 loops Example: n=8

t

slide-5
SLIDE 5

Institute for Applied Information Processing and Communications (IAIK) 5

TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011

Operand Scanning

“Schoolbook method”

a * b = c

Row-wise processing 2 loops Example: n=8

t

slide-6
SLIDE 6

Institute for Applied Information Processing and Communications (IAIK) 6

TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011

Operand Scanning

“Schoolbook method”

a * b = c

Row-wise processing 2 loops Example: n=8

t

slide-7
SLIDE 7

Institute for Applied Information Processing and Communications (IAIK) 7

TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011

Operand Scanning

“Schoolbook method”

a * b = c

Row-wise processing 2 loops Example: n=8

t

slide-8
SLIDE 8

Institute for Applied Information Processing and Communications (IAIK) 8

TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011

Operand Scanning

“Schoolbook method”

a * b = c

Row-wise processing 2 loops Example: n=8

t

slide-9
SLIDE 9

Institute for Applied Information Processing and Communications (IAIK) 9

TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011

Product Scanning

slide-10
SLIDE 10

Institute for Applied Information Processing and Communications (IAIK) 10

TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011

Hybrid Multiplication

d f=3d+2

slide-11
SLIDE 11

Institute for Applied Information Processing and Communications (IAIK) 11

TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011

Operand-Caching Multiplication

binit

slide-12
SLIDE 12

Institute for Applied Information Processing and Communications (IAIK) 12

TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011

Operand-Caching Multiplication

Row 0

slide-13
SLIDE 13

Institute for Applied Information Processing and Communications (IAIK) 13

TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011

Operand-Caching Multiplication

Row 1

slide-14
SLIDE 14

Institute for Applied Information Processing and Communications (IAIK) 14

TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011

Operand-Caching Multiplication

e f=2e+3

slide-15
SLIDE 15

Institute for Applied Information Processing and Communications (IAIK) 15

TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011

Operand-Caching Multiplication

Part 1

slide-16
SLIDE 16

Institute for Applied Information Processing and Communications (IAIK) 16

TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011

Operand-Caching Multiplication

Part 2

slide-17
SLIDE 17

Institute for Applied Information Processing and Communications (IAIK) 17

TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011

Operand-Caching Multiplication

Part 3

slide-18
SLIDE 18

Institute for Applied Information Processing and Communications (IAIK) 18

TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011

Operand-Caching Multiplication

Part 4

slide-19
SLIDE 19

Institute for Applied Information Processing and Communications (IAIK) 19

TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011

Complexity

slide-20
SLIDE 20

Institute for Applied Information Processing and Communications (IAIK) 20

TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011

Results

160-bit multiplication on the ATmega128 Unrolled instructions

slide-21
SLIDE 21

Institute for Applied Information Processing and Communications (IAIK) 21

TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011

Comparison with Related Work

Note: Scott et al. unrolled the instructions

slide-22
SLIDE 22

Institute for Applied Information Processing and Communications (IAIK) 22

TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011

Let‘s summarize… …it‘s faster…

slide-23
SLIDE 23

Institute for Applied Information Processing and Communications (IAIK) 23

TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011

Let‘s summarize… …it’s more energy efficient…

slide-24
SLIDE 24

Institute for Applied Information Processing and Communications (IAIK) 24

TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011

Let‘s summarize… …it outperforms existing solutions!

slide-25
SLIDE 25

Institute for Applied Information Processing and Communications (IAIK) 25

TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011

Thank you!

Michael Hutter

IAIK – Graz University of Technology michael.hutter@iaik.tugraz.at www.iaik.tugraz.at

slide-26
SLIDE 26

Institute for Applied Information Processing and Communications (IAIK) 26

TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011

Recent Results

Performance on the 32-bit ARM 7 192-bit multiplication 441 clock cycles needed 10% improvement compared to related work

Scott et al. reported 487 cycles

slide-27
SLIDE 27

Institute for Applied Information Processing and Communications (IAIK) 27

TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011

Memory-Access Complexity

slide-28
SLIDE 28

Institute for Applied Information Processing and Communications (IAIK) 28

TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011

Performance for Larger Integers

slide-29
SLIDE 29

Institute for Applied Information Processing and Communications (IAIK) 29

TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011

Available Registers

slide-30
SLIDE 30

Institute for Applied Information Processing and Communications (IAIK) 30

TU Graz/Computer Science/IAIK/SEnSE Nara, 01.10.2011 CHES 2011

160-bit Multiplication