From Simulink to NoC-based MPSoC on FPGA Simulink front-end for the - - PowerPoint PPT Presentation

From Simulink to NoC-based MPSoC on FPGA

Simulink front-end for the NoC System Generator (NSG) Francesco Robino

KTH Royal Institute of Technology

ICES seminar

• F. Robino (KTH)

From Simulink to MPSoC on FPGA 20-05-2014 1 / 17

Overview of the talk

Motivation

What is the problem? Our goal

Reaching the goal

Simulink simulation semantics The HeartBeat (HB) model in a MPSoC generated by NSG Connecting Simulink and HB NoC-based MPSoC semantics Experimental evidences and results

Conclusion

• F. Robino (KTH)

From Simulink to MPSoC on FPGA 20-05-2014 2 / 17

The problem

Matlab/Simulink is today’s de-facto standard for model-based design in domains such as control engineering and signal processing. NoC-based MPSoCs are promising candidates for future embedded system (potentially high performances, low power consumption,. . . ). Synthesis of a Simulink model onto NoC-based MPSoCs is still an

• pen issue.

P e P e P e P e P e P e Application Instance Platform Instance

• F. Robino (KTH)

From Simulink to MPSoC on FPGA 20-05-2014 3 / 17

Our goal

To enable an end-to-end design flow, we follow the principles of the platform-based design methodology, constraining platform (MPSoC) and functionality (Simulink model) to share a common semantic domain.

P e P e P e P e P e P e

Application Instance Platform Instance Common semantics domain

• F. Robino (KTH)

From Simulink to MPSoC on FPGA 20-05-2014 4 / 17

Simulink: an environment for system-level design

A Simulink model is graphically described through the use of blocks (e.g. an adder, a transfer function, etc.) and subsystems (a set of blocks), linked by signals. Using different blocks and subsystems, architecture and application specification can be combined in a mixed HW/SW model.

• F. Robino (KTH)

From Simulink to MPSoC on FPGA 20-05-2014 5 / 17

Solvers and Simulink simulation semantics

Initialization

Simulation stop time?

Start simulation Y N Store inputs Compute outputs Generate outputs Advance simulation time Stop simulation

Simulation loop

Simulink simulates a dynamic system by computing its states at successive time steps over a specified time span, using information provided by the model. A solver determines the time of the next simulation step and applies a numerical method to solve the set of ordinary differential equations (ODEs) that represent the model. Different solvers embody different approaches to solve a model.

• F. Robino (KTH)

From Simulink to MPSoC on FPGA 20-05-2014 6 / 17

Solvers and Simulink simulation semantics

Initialization

Simulation stop time?

Start simulation Y N Store inputs Compute outputs Generate outputs Advance simulation time Stop simulation

Simulation loop

Solvers: fixed-step VS variable-step

0 0.25 0.5 0.75 S0 S0 S1 S2 1 1.25 1.5 1.75 S3 S3 S4 S4 0.5 0.75 S0 S1 S2 1 1.5 S3 S4

discrete VS continuous

Continuous: compute model’s continuous states at the current time from the states at previous time steps and the state derivatives (requires ordinary differential equations).

• ne-step VS multi-step

One-step solvers estimate y(tn) using only the solution at the preceding time point y(tn−1) Multistep solvers use the results at several preceding time steps to compute the solution

• F. Robino (KTH)

From Simulink to MPSoC on FPGA 20-05-2014 7 / 17

Solvers and Simulink simulation semantics

Initialization

Simulation stop time?

Start simulation Y N Store inputs Compute outputs Generate outputs Advance simulation time Stop simulation

Simulation loop

Our approach today targets the following solver configuration: fixed-step (constant step size tstep) discrete

• ne-step

However, it can be extended to other solvers too. . .

• F. Robino (KTH)

From Simulink to MPSoC on FPGA 20-05-2014 8 / 17

Simulink Embedded Coder

Execute rt_onestep Interrupt received? Begin

Y N

PE SW Initialize SW processes Wait first interrupt Interrupt

When we select a fixed-step solver, we can use the Simulink Embedded Coder to generate C code of the model for use on embedded processors. The code generated include: Main scheduler sensitive on interrupt. rt onestep function, implemented in the interrupt service routine (ISR), describing the functionality of the system. The generated software is compliant with the execution model of the Simulink simulation!

• F. Robino (KTH)

From Simulink to MPSoC on FPGA 20-05-2014 9 / 17

The HeartBeat model in a MPSoC generated by NSG

Execute SW processes HB tick received? Begin

Y N

PE HB tick SW Initialize SW processes Wait first HB tick

P E P E 1 P E 2 P E 3

1 2 3 3 6 5 8 PE 0

NoC

H B p e r i

• d

H B t i c k s ε c

1 2 3 7

NoC

ε c

1 2 8

NoC

ε c

4 3 1 2 9

NoC

ε c

4 3 5 PE 1 PE 2 PE 3

N

• C

S y s t e m G e n e r a t

• r

process network and system specs

H B p r

• c

e s s w r a p p e r S i m u l i n k m

• d

e l

• F. Robino (KTH)

From Simulink to MPSoC on FPGA 20-05-2014 10 / 17

Connecting Simulink and HB NoC-based MPSoC semantics

Simulink

Initialization Simulation stop time? Start simulation Y N Store inputs Compute outputs Generate outputs Advance simulation time Stop simulation Simulation loop

• Emb. Coder

Execute rt_onestep Interrupt received? Begin

Y N

P E S W Initialize SW processes Wait first interrupt Interrupt

HeartBeat

Execute SW processes HB tick received? Begin

Y N

P E HB tick S W Initialize SW processes Wait first HB tick

Table: Common semantics parameters and design rules

Simulink HB compliant MPSoC time steps HB ticks step size (tstep) HB period (tHB) simulation loop SW processes triggered by HB wrapper rt onestep SW running on one PE blocks instructions of SW process subsystem SW processes on a single PE (rt onestep) signal NoC communication path

Application Instance Platform Instance

• F. Robino (KTH)

From Simulink to MPSoC on FPGA 20-05-2014 11 / 17

Case study: DSP system (Digital FIR filter)

http://www.mathworks.se/help/dsp/ug/digital-filter-block.html

• F. Robino (KTH)

From Simulink to MPSoC on FPGA 20-05-2014 12 / 17

Case study: Embedded coder vs SLD HB methodology

P E P E P E 1 P E 2 P E 3

• F. Robino (KTH)

From Simulink to MPSoC on FPGA 20-05-2014 13 / 17

Case study: results

Table: WCET, minimum tHB, memory requirements

1 PE 4 PEs Source Noise Filter Sink WCET - Min. tHB [ms] 28 7,90 11,68 8,00 0,01

• Mem. req. w/o OS [KB]

53 33 27 21 16

• Mem. req. eCos [KB]

+20 +20 for each PE

• Mem. req. uCLinux [MB]

+2 +2 for each PE

Splitting the system in 4 subsystems using this methodology, increases the throughput of the system of ca 2.4×. If we would have created 4 subsystems having equal WCET (i.e. 7 ms), we could have reached a theoretical 4× throughput increase. The increase in throughput comes at the expense of memory.

• F. Robino (KTH)

From Simulink to MPSoC on FPGA 20-05-2014 14 / 17

Case study: semantics preserving?

[0.00003,0.00006,

• 0.001011,-0.006998,...]

[0.000000,0.453990, 0.809017,0.987688,...] [X,-0.014091, 0.043682,0.440711,...] [X,X, 0.00003,0.00006,...] [0.043682,0.440711,...] [0.00003,0.00006,...] [0.809017,0.987688,...]

• F. Robino (KTH)

From Simulink to MPSoC on FPGA 20-05-2014 15 / 17

Conclusions

We have described a system-level design flow that allows the synthesis of Simulink models to NoC-based MPSoCs, generating a working prototype on low-cost FPGAs. The generated MPSoC is constrained to share a common semantics domain with the Simulink model, so that the results between simulation and implementation of the prototype are the same, without the need of resource consuming SW components (such as OS). Design methodology based on process constructors — HB process wrappers to provide execution semantics to the MPSoC. Developed a synthesis methodology with similarities with synchronous HW design

Minimize HB period tHB . Exploits task, data and pipeline parallelism.

• F. Robino (KTH)

From Simulink to MPSoC on FPGA 20-05-2014 16 / 17

Questions?

Suggestions: Can this approach be extended to other Simulink solvers? Does this approach provide real-time guarantees?

No OS overhead Quite precise measurement of WCET When no shared connections, quite precise (and not pessimistic) WCCT

Why not everything asynchronous1? (see asynchronous CPUs)

1Asynchronous circuits are not governed by a global clock, but they use signals to

indicate completion of instructions and operations, specified by data transfer protocols.

• F. Robino (KTH)

From Simulink to MPSoC on FPGA 20-05-2014 17 / 17