I I I -Vs for CMOS Beyond Silicon J. A. del Alamo Microsystems - - PowerPoint PPT Presentation

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I I I -Vs for CMOS Beyond Silicon

• J. A. del Alamo

Microsystems Technology Laboratories, MIT

Acknowledgements:

• D. Antoniadis, A. Guo, D.-H. Kim, T.-W. Kim, D. Jin, J. Lin, N. Waldron, L. Xia
• Sponsors: Intel, FCRP-MSD
• Labs at MIT: MTL, NSL, SEBL

MIT Lincoln Laboratory Advanced Research and Technology Symposium

February 26-27, 2013

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Bipolar/E-D PHEMT process

Henderson, Mantech 2007 40 Gb/s modulator driver Tessmann, GaAs IC 1999 77 GHz transceiver Carroll, MTT-S 2002 UMTS-LTE PA module Chow, MTT-S 2008 Single-chip WLAN MMIC, Morkner, RFIC 2007

I I I -V HEMT Electronics Today

I I I -V HEMT: record fT vs. time

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• For >20 years, record fT obtained on InGaAs-channel HEMTs
• InGaAs-channel HEMTs offer record balanced fT and fmax

Current record: fT=688 GHz fmax=800 GHz Kim IEDM 2011 (Teledyne/MIT)

Devices fabricated at MIT

S D

Etch stopper

Barrier Channel Buffer t

ins

Oxide

t ch

Gate

Cap

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I nAlAs/ I nGaAs HEMTs at MI T

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• QW channel (tch = 10 nm):
• InAs core
• InGaAs cladding

 n,Hall = 13,200 cm2/V-sec

• InAlAs barrier (tins = 4 nm)
• Lg=30 nm

Kim, EDL 2010

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Lg= 30 nm I nGaAs HEMT

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• High transconductance: gmpk= 1.9 mS/μm at VDD=0.5 V
• First transistor of any kind with both fT and fmax > 640 GHz

(current record is fT, fmax>688 GHz in Teledyne/MIT collaboration)

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Kim, EDL 2010

• 0.6
• 0.4
• 0.2

0.0 0.2 0.0 0.5 1.0 1.5 2.0

gm [mS/m] VGS [V]

VDS = 0.5 V

0.0 0.2 0.4 0.6 0.8 0.0 0.2 0.4 0.6 0.8

0.2 V 0.4 V 0 V

ID [mA/m] VDS [V]

VGS =

10

9

10

10

10

11

10

12

10 20 30 40

Frequency [Hz] Gains [dB]

• 1

1 2 3

K

H21 K MSG/MAG Ug

VDS=0.5 V, VGS=0.2 V

EC vinj

• vinj(InGaAs) increases with InAs fraction in channel
• vinj(InGaAs) > 2vinj(Si) at less than half VDD
• ~100% ballistic transport at Lg~30 nm

I nGaAs Electron I njection Velocity

Kim, IEDM 2009 Liu, Springer 2010 Khakifirooz, TED 2008 del Alamo, Nature 2011

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EV

Self-Aligned I nGaAs QW-MOSFETs

• Scaled barrier (InP: 1 nm + HfO2: 2 nm) [EOT~0.8 nm]
• 10 nm thick channel with InAs core
• Tight S/D spacing (Lside =20~30 nm)
• Process designed to be compatible with Si fab

Lin, IEDM 2012

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Lside

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Lg= 30 nm Self-aligned QW-MOSFET

At VDS=0.5 V:

• gm = 1.4 mS/µm
• S=114 mV/dec
• Ig<1 nA/µm
• Ron = 470 m

Lin, IEDM 2012

• 0.4
• 0.2

0.0 0.2 10

• 8

10

• 7

10

• 6

10

• 5

10

• 4

10

• 3

S (mV/dec)

50 mV

ID (A/m) VGS (V)

VDS=0.5 V

Lg=30 nm

80 120 160 200 240 280 320

Scaling and benchmarking

• Superior behavior to any planar III-V MOSFET to date
• Matches performance of III-V Trigate MOSFETs

[Radosavljevic, IEDM 2011]

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40 80 120 160 100 200 300 400 500

MIT HEMT Planar Trigate This work

Ion (A/m) Lg (nm)

III-V FETs

Ioff=100 nA/m VDD=0.5 V

Lin, IEDM 2012

Long-channel I nGaAs MOSFET

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• S=69 mV/dec at VDS=50 mV
• Close to lowest S reported in any III-V MOSFET: 66 mV/dec

(EOT=1.2 nm) [Radosavljevic, IEDM 2011]

InP (1 nm) + Al2O3 (0.4 nm) + HfO2 (2 nm)  EOT~0.9 nm Lin, IEDM 2012

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Ongoing research

• N-channel InGaAs MOSFETs:

– Planar InGaAs MOSFET with improved access region for reduced resistance – Trigate InGaAs MOSFET with self-aligned contacts – Nanowire MOSFET with enhanced subthreshold swing – Ohmic contacts to InGaAs MOSFET

• P-channel InGaSb MOSFETs:

– Planar InGaSb MOSFET with uniaxial compressive strain for enhanced hole transport – Ohmic contacts to InGaSb MOSFET