On On On On On On On On CMOS Circuit CMOS Circuit CMOS - - PowerPoint PPT Presentation

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On On On On On On On On CMOS Circuit CMOS Circuit CMOS - - PowerPoint PPT Presentation

Jun 29, 2023 173 likes •412 views

6.2009 .2009 6.2009 .2009 On On On On On On On On CMOS Circuit CMOS Circuit CMOS Circuit CMOS Circuit CMOS Circuit CMOS Circuit CMOS Circuit CMOS Circuit 29.06 29.06 29.0 29.0 Reliability Reliability Reliability

slide-1
SLIDE 1

On On On On On On On On

6.2009 .2009 6.2009 .2009

CMOS Circuit CMOS Circuit CMOS Circuit CMOS Circuit Reliability liability Reliability liability CMOS Circuit CMOS Circuit CMOS Circuit CMOS Circuit Reliability liability Reliability liability

29.0 29.06 29.0 29.06

Reliability liability Reliability liability Reliability liability Reliability liability

tug ugal al tug ugal al •

from from from from

il, Por l, Port il, Por l, Port

T

Estor Estori Estor Estori

The he The he MOSFET MOSFETs MOSFET MOSFETs

N’09 N’09 N’09 N’09 •

  • MOSFET

MOSFETs MOSFET MOSFETs and the and the and the and the

SN/DS SN/DS SN/DS SN/DS

Inp Input V ut Vectors ctors Inp Input V ut Vectors ctors

Va Valeriu Va Valeriu Beiu

Beiu Beiu Beiu and and and and Walid Ibr alid Ibrahim him Wa Walid I Ibrahim

WD WD WD WD

slide-2
SLIDE 2

6.2009 .2009 6.2009 .2009

Structure o tructure of the the presentation resentation Structure o tructure of the the presentation resentation

29.0 29.06 29.0 29.06

f p f p f p f p

Classical view

Classical view

tug ugal al tug ugal al •

Ubiquitous … variations

Ubiquitous … variations

  • Thermal

Thermal

il, Por l, Port il, Por l, Port

  • Leakage

Leakage

  • Vdd

Vdd

Estor Estori Estor Estori

  • Fabrication …

Fabrication …

Detailed (atomistic) view

Detailed (atomistic) view

N’09 N’09 N’09 N’09 •

  • (

) ( )

Vth variations

Vth variations

Gate

Gate level simulations level simulations

SN/DS SN/DS SN/DS SN/DS

Gate

Gate-level simulations level simulations

Conclusions

Conclusions

WD WD WD WD

2

slide-3
SLIDE 3

6.2009 .2009 6.2009 .2009

Classical view Classical view Classical view Classical view

29.0 29.06 29.0 29.06 tug ugal al tug ugal al •

90 90 65 65 45 45 32 32 22 22 DRAM ½ pitch DRAM ½ pitch

il, Por l, Port il, Por l, Port

100nm 100nm 90 90 65 65 45 45 32 32 22 22 16 16 Logic Generation Logic Generation 130 130

Estor Estori Estor Estori

75nm 75nm

New material New material

N’09 N’09 N’09 N’09 •

  • 50nm

50nm

High High-

  • k

k Metal gate Metal gate for strained for strained-

  • Si

Si

Cutline B Cutline B-
  • B’
B’

Si Si

S D G

Si Si

S D G S D G BOX BOX

HfSiON HfSiON

SN/DS SN/DS SN/DS SN/DS

25nm 25nm

Metal gate Metal gate Double gate Double gate 3D FinFET 3D FinFET

BOX BOX

WD WD WD WD

3

‘00 ‘00 ‘05 ‘05 ‘10 ‘10 ‘15 ‘15 ‘20 ‘20

From Samsung From Samsung

slide-4
SLIDE 4

6.2009 .2009 6.2009 .2009

Variations … thermal ariations … thermal Variations … thermal ariations … thermal

29.0 29.06 29.0 29.06 tug ugal al tug ugal al • il, Por l, Port il, Por l, Port Estor Estori Estor Estori N’09 N’09 N’09 N’09 •

  • SN/DS

SN/DS SN/DS SN/DS WD WD WD WD

4

slide-5
SLIDE 5

6.2009 .2009 6.2009 .2009

Variations … leaka ariations … leakage Variations … leaka ariations … leakage

29.0 29.06 29.0 29.06

g

tug ugal al tug ugal al • il, Por l, Port il, Por l, Port Estor Estori Estor Estori N’09 N’09 N’09 N’09 •

  • SN/DS

SN/DS SN/DS SN/DS WD WD WD WD

5

slide-6
SLIDE 6

6.2009 .2009 6.2009 .2009

Variations … Vdd ariations … Vdd Variations … Vdd ariations … Vdd

29.0 29.06 29.0 29.06 tug ugal al tug ugal al • il, Por l, Port il, Por l, Port Estor Estori Estor Estori N’09 N’09 N’09 N’09 •

  • SN/DS

SN/DS SN/DS SN/DS WD WD WD WD

6

slide-7
SLIDE 7

6.2009 .2009 6.2009 .2009

Vdd noise (Itanium, 90nm) dd noise (Itanium, 90nm) Vdd noise (Itanium, 90nm) dd noise (Itanium, 90nm)

29.0 29.06 29.0 29.06 tug ugal al tug ugal al • il, Por l, Port il, Por l, Port Estor Estori Estor Estori N’09 N’09 N’09 N’09 •

  • SN/DS

SN/DS SN/DS SN/DS WD WD WD WD

7

  • S. Naffziger, B. Stackhouse, T. Grutkowski, D. Josephson, J. Desai, E. Alon, and M. Horowitz

The Implementation of a 2-Core, Multi-Threaded Itanium Family Processor, J. Solid-State Circ., Jan. 2006

slide-8
SLIDE 8

6.2009 .2009 6.2009 .2009

Variations … when ariations … when fabricatin abricating Variations … when ariations … when fabricatin abricating

29.0 29.06 29.0 29.06

f g f g f g f g

tug ugal al tug ugal al • il, Por l, Port il, Por l, Port Estor Estori Estor Estori N’09 N’09 N’09 N’09 •

  • SN/DS

SN/DS SN/DS SN/DS WD WD WD WD

8

  • S. Nassif, DAC’03
  • S. Nassif, DAC’03
slide-9
SLIDE 9

6.2009 .2009 6.2009 .2009

Variations … mis ariations … misplacin lacing atoms atoms Variations … mis ariations … misplacin lacing atoms atoms

29.0 29.06 29.0 29.06

p g p g p g p g

tug ugal al tug ugal al • il, Por l, Port il, Por l, Port Estor Estori Estor Estori N’09 N’09 N’09 N’09 •

  • SN/DS

SN/DS SN/DS SN/DS WD WD WD WD

9

slide-10
SLIDE 10

6.2009 .2009 6.2009 .2009

Detailed view (atomistic) etailed view (atomistic) Detailed view (atomistic) etailed view (atomistic)

29.0 29.06 29.0 29.06 tug ugal al tug ugal al • il, Por l, Port il, Por l, Port Estor Estori Estor Estori

35nm 35nm 22 22

N’09 N’09 N’09 N’09 •

  • 22nm

22nm

SN/DS SN/DS SN/DS SN/DS

4.2nm 4.2nm

WD WD WD WD

10 10

slide-11
SLIDE 11

6.2009 .2009 6.2009 .2009

Countin Counting e e Countin Counting e e– …

29.0 29.06 29.0 29.06

g

tug ugal al tug ugal al • il, Por l, Port il, Por l, Port Estor Estori Estor Estori N’09 N’09 N’09 N’09 •

  • SN/DS

SN/DS SN/DS SN/DS WD WD WD WD

11 11

  • E. Pop: Movie of an 18nm ultra
  • E. Pop: Movie of an 18nm ultra-
  • thin body SOI, MONET & Medici (energy in

thin body SOI, MONET & Medici (energy in eV eV on the right bar)

  • n the right bar)
slide-12
SLIDE 12

6.2009 .2009 6.2009 .2009

Vth variations th variations Vth variations th variations

29.0 29.06 29.0 29.06

Keyes

Keyes 1975 1975

tug ugal al tug ugal al •

Hagigava et al.

Hagigava et al. 1982 1982

Wong & Taur

Wong & Taur 1993 1993

il, Por l, Port il, Por l, Port

g

Mizuno et al.

Mizuno et al. 1994 1994

Wong et al

Wong et al 1998 1998

Estor Estori Estor Estori

Wong et al.

Wong et al. 1998 1998

Asenov

Asenov 1998 1998

N’09 N’09 N’09 N’09 •

  • Random dopants, oxide thickness variations, line

Random dopants, oxide thickness variations, line

SN/DS SN/DS SN/DS SN/DS

edge roughness, polysilicon granularity, interface edge roughness, polysilicon granularity, interface roughness, high roughness, high-

  • k morphology

morphology

WD WD WD WD

12 12

σ =

= tox

  • x NA

0.45 0.45 / (

/ (Leff

effWeff eff)1/2 1/2

slide-13
SLIDE 13

6.2009 .2009 6.2009 .2009

Latest atest Latest atest

29.0 29.06 29.0 29.06

results results results results fro fro fro fro

tug ugal al tug ugal al •

fro from fro from Asenov’s senov’s Asenov’s senov’s

il, Por l, Port il, Por l, Port

A group group group group

Estor Estori Estor Estori N’09 N’09 N’09 N’09 •

  • SN/DS

SN/DS SN/DS SN/DS WD WD WD WD

13 13

slide-14
SLIDE 14

6.2009 .2009 6.2009 .2009

From From From From

29.0 29.06 29.0 29.06

MOS OS MOS OS to to to to

tug ugal al tug ugal al •

to to to to gates ates gates ates

il, Por l, Port il, Por l, Port

g

Estor Estori Estor Estori N’09 N’09 N’09 N’09 •

  • SN/DS

SN/DS SN/DS SN/DS WD WD WD WD

14 14

slide-15
SLIDE 15

6.2009 .2009 6.2009 .2009

Devices evices Devices evices

29.0 29.06 29.0 29.06

get into et into get into et into the the pi ture ure the the pi ture ure

tug ugal al tug ugal al •

the the pi picture ture the the pi picture ture

il, Por l, Port il, Por l, Port Estor Estori Estor Estori N’09 N’09 N’09 N’09 •

  • SN/DS

SN/DS SN/DS SN/DS WD WD WD WD

15 15

  • V. Beiu
  • V. Beiu et al.

et al., , IWANN’07 IWANN’07, 2007 , 2007

slide-16
SLIDE 16

6.2009 .2009 6.2009 .2009

Probabilit robability densit density functions unctions Probabilit robability densit density functions unctions

29.0 29.06 29.0 29.06

y y y y f y y y y f

tug ugal al tug ugal al • il, Por l, Port il, Por l, Port Estor Estori Estor Estori N’09 N’09 N’09 N’09 •

  • SN/DS

SN/DS SN/DS SN/DS WD WD WD WD

16 16

slide-17
SLIDE 17

6.2009 .2009 6.2009 .2009

nMOS … Vth at Vdd/2, /3, /4 MOS … Vth at Vdd/2, /3, /4 nMOS … Vth at Vdd/2, /3, /4 MOS … Vth at Vdd/2, /3, /4

29.0 29.06 29.0 29.06 tug ugal al tug ugal al • il, Por l, Port il, Por l, Port Estor Estori Estor Estori N’09 N’09 N’09 N’09 •

  • SN/DS

SN/DS SN/DS SN/DS WD WD WD WD

17 17

slide-18
SLIDE 18

6.2009 .2009 6.2009 .2009

Inverter (noise at Vdd/3, /4, /5 …) nverter (noise at Vdd/3, /4, /5 …) Inverter (noise at Vdd/3, /4, /5 …) nverter (noise at Vdd/3, /4, /5 …)

29.0 29.06 29.0 29.06 10 tug ugal al tug ugal al • re il, Por l, Port il, Por l, Port 10

−5

y of failur Estor Estori Estor Estori robability N’09 N’09 N’09 N’09 •

  • 10

−10

INV Pr SN/DS SN/DS SN/DS SN/DS 10

−15

WD WD WD WD

18 18

5 10 15 20 25 30 35 40 45 10

15

Feature size [nm]

slide-19
SLIDE 19

6.2009 .2009 6.2009 .2009

NAND AND NAND AND-2 2 2 2

29.0 29.06 29.0 29.06 10 tug ugal al tug ugal al • ailure il, Por l, Port il, Por l, Port 10

−5

lity of Fa Estor Estori Estor Estori

10

2 probabi N’09 N’09 N’09 N’09 •

  • 10

−10

NAND−2 SN/DS SN/DS SN/DS SN/DS 10

−15

WD WD WD WD

19 19

5 10 15 20 25 30 35 40 45 10 Feature size[nm]

slide-20
SLIDE 20

6.2009 .2009 6.2009 .2009

NAND AND NAND AND-2 … 3D view 2 … 3D view 2 … 3D view 2 … 3D view

29.0 29.06 29.0 29.06 1 tug ugal al tug ugal al • 1E−5 1 ailure il, Por l, Port il, Por l, Port 1E−10 bility of fa Estor Estori Estor Estori 1E−15 2 probab N’09 N’09 N’09 N’09 •

  • 1E−20

NAND−2 SN/DS SN/DS SN/DS SN/DS 200 400 500 1E−25 WD WD WD WD

20 20

200 400 600 800 1000 500 1000 Input−1 [mV] Input−2 [mV]

slide-21
SLIDE 21

6.2009 .2009 6.2009 .2009

Inverter … 2, 1.99, 1.98. 1.97 nverter … 2, 1.99, 1.98. 1.97 Inverter … 2, 1.99, 1.98. 1.97 nverter … 2, 1.99, 1.98. 1.97

29.0 29.06 29.0 29.06 10 tug ugal al tug ugal al • 10

−2

re il, Por l, Port il, Por l, Port 10

−4

  • f failu

Estor Estori Estor Estori 10

−6

  • bability

N’09 N’09 N’09 N’09 •

  • 10

10

−8

INV pro SN/DS SN/DS SN/DS SN/DS 10

−12

10

−10

WD WD WD WD

21 21

200 400 600 800 10 Input voltage [mV]

slide-22
SLIDE 22

6.2009 .2009 6.2009 .2009

Inverter 3D (at 1.97) nverter 3D (at 1.97) Inverter 3D (at 1.97) nverter 3D (at 1.97)

1E 10 1E−5 1 ty of failure

29.0 29.06 29.0 29.06

1E−25 1E−20 1E−15 1E−10 NAND−2 probabilit

tug ugal al tug ugal al • 1 ailure

200 400 600 800 1000 500 1000 Input−1 [mV] Input−2 [mV]

il, Por l, Port il, Por l, Port 1E−4 1E−2 bility of fa Estor Estori Estor Estori 1E−8 1E−6 −2 probab N’09 N’09 N’09 N’09 •

  • 1E−12

1E−10 NAND− SN/DS SN/DS SN/DS SN/DS 400 600 800 200 400 WD WD WD WD

22 22

200 400 400 600 800 Input−2 [mV] Input−1 [mV]

slide-23
SLIDE 23

6.2009 .2009 6.2009 .2009 29.0 29.06 29.0 29.06 tug ugal al tug ugal al • il, Por l, Port il, Por l, Port Estor Estori Estor Estori N’09 N’09 N’09 N’09 •

  • SN/DS

SN/DS SN/DS SN/DS WD WD WD WD

23 23