[PPT] - Introduction to Metal FS and FPGA Programming Hands-On Robert Schmid PowerPoint Presentation

SLIDE 1

Introduction to Metal FS and FPGA Programming Hands-On

Robert Schmid, Max Plauth, Sven Köhler, Lukas Wenzel and Andreas Polze Operating Systems and Middleware Group 19.06.2019

SLIDE 2

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Field-Programmable Gate Array: programmable hardware circuit

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Algorithms are represented as a hardware configuration

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Reasons for using FPGAs

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Energy efficiency

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Parallel and pipelined data processing

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‘Computing wires’

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Technology Advancements

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New Generation of Interconnects (OpenCAPI, CCIX, ...)

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High-Level Synthesis (HLS) languages

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‘Accelerators become first-class citizens in the system’

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Interest in FPGAs is growing (again)

Programmable Interconnect Logic Blocks IO Blocks RAM/ALU/... Blocks

SLIDE 3

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How should end-users interact with FPGAs?

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Just like with any other executable program!

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Analogy: Builtin UNIX tools (cat, grep, sed, awk, …)

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Do one thing, and do it well!

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First-class citizens?

UNIX Pipe Redirect Standard Output to File

$ echo "Hello World" | fpga-encrypt –k key.bin > encrypted_file.bin

‘Operator’

SLIDE 4

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Goal: Improve the accessibility of FPGA accelerators using a file system abstraction

Foundations

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Metal FS

IBM POWER CAPI + SNAP Xilinx Vivado

SLIDE 5

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Operators are specified in Vivado HLS

void my_metal_operator(mtl_stream & in, mtl_stream & out, snapu64_t offset) { mtl_stream_element element; do { element = in.read(); element.data += offset;

ut.write(element);

} while (!element.last); }

Operator

Configuration Input Stream Output Stream

ParProg 2019 Metal FS

SLIDE 6

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What happens here?

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In between FPGA processing steps, data should not be copied to the CPU’s main memory (slow)

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In conclusion:

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Multiple operators must be deployed on the FPGA at once

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Active subset and order of Operators should be configurable at runtime

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Chaining Operators

$ cat encrypted_file.bin | fpga-decrypt | fpga-uppercase HELLO WORLD

SLIDE 7

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Streaming Data from different types of memory

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Metal FS Operator Pipelines

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Composition of Pipelines by using AXI Stream Switch

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C++ API

Stream Switch Blowfish Encrypt Blowfish Decrypt Change Case Host Memory Non- volatile Memory No-op

OperatorRegistry registry; auto encrypt = registry.operators().at("encrypt"); encrypt->setOption("key", keyBuffer); auto dataSource = create_data_source(inputBuffer); auto dataSink = create_data_sink(outputBuffer); PipelineDefinition pipeline ({ dataSource, encrypt, dataSink }); pipeline.run();

SLIDE 8

ap_clk ap_rst_n s_axi_ctrl_reg axi_metal_cpc AXI Protocol Converter S_AXI M_AXI aclk aresetn axi_metal_ctrl_crossbar AXI Crossbar S00_AXI M00_AXI M01_AXI M02_AXI M03_AXI M04_AXI aclk aresetn

p_colorfilter

Hls_operator_colorfilter (Pre-Production) s_axi_control axis_input axis_output ap_clk ap_rst_n interrupt axi_datamover_mm2s AXI DataMover M_AXI_MM2S S_AXIS_MM2S_CMD M_AXIS_MM2S_STS M_AXIS_MM2S m_axi_mm2s_aclk m_axi_mm2s_aresetn mm2s_err m_axis_mm2s_cmdsts_aclk m_axis_mm2s_cmdsts_aresetn hls_streamgen Hls_streamgen (Pre-Production) s_axi_ctrl

ut_r

ap_clk ap_rst_n interrupt metal_switch AXI4-Stream Switch S00_AXIS M00_AXIS S01_AXIS M01_AXIS S_AXI_CTRL aclk aresetn s_axi_ctrl_aclk s_axi_ctrl_aresetn interrupt_zero Constant dout[0:0] data_selector AXI4-Stream Switch S00_AXIS M00_AXIS S01_AXIS M01_AXIS S02_AXIS M02_AXIS S_AXI_CTRL aclk aresetn s_axi_ctrl_aclk s_axi_ctrl_aresetn axi_perf_mon_0 AXI Performance Monitor S_AXI SLOT_0_AXIS SLOT_1_AXIS s_axi_aclk s_axi_aresetn slot_0_axis_aclk slot_0_axis_aresetn slot_1_axis_aclk slot_1_axis_aresetn capture_event reset_event core_aclk core_aresetn interrupt interrupt_concat Concat In0[0:0] In1[0:0] In2[0:0] In3[0:0] In4[0:0] In5[0:0] In6[0:0] In7[0:0] dout[7:0] axi_streamsink Hls_streamsink (Pre-Production) data ap_clk ap_rst_n axi_datamover_s2mm AXI DataMover M_AXI_S2MM S_AXIS_S2MM S_AXIS_S2MM_CMD M_AXIS_S2MM_STS m_axi_s2mm_aclk m_axi_s2mm_aresetn s2mm_err m_axis_s2mm_cmdsts_awclk m_axis_s2mm_cmdsts_aresetn

ne

Constant dout[0:0] dm_smartconnect AXI SmartConnect S00_AXI S01_AXI M00_AXI aclk aresetn snap_action Hls_action (Pre-Production) s_axi_ctrl_reg m_axi_host_mem mm2s_cmd_V_V mm2s_sts s2mm_cmd_V_V s2mm_sts m_axi_metal_ctrl_V interrupt_reg_V_V interrupt_reg_V_V_TVALID interrupt_reg_V_V_TDATA[7:0] ap_clk ap_rst_n interrupt axi_host_mem_crossbar AXI Crossbar S00_AXI M00_AXI S01_AXI aclk aresetn m_axi_host_mem interrupt

Composition of Hardware Components: Block Design

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SLIDE 9

Foundations

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Metal FS: Architecture Overview

CPU (‘Host’) FPGA Operator Pipelines Operator Pipelines IBM POWER CAPI + SNAP Xilinx Vivado

Operator Pipelines

AXI Stream Switch C++ API

SLIDE 10

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Leverage the NVMe storage on the Nallatech N250S FPGA card

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One use case for Operator Pipelines

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File System Metadata is maintained in an LMDB Key-Value Store on the host

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inodes, directory entries, free extents

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Block Mapper on the FPGA translates file offsets to physical addresses using extent lists

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All file accesses are implemented as Operator Pipelines (Read -> Write)

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Data transformations can be transparently added (e.g. encryption)

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Metal FS Hybrid Filesystem

SLIDE 11

Foundations

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Metal FS: Architecture Overview

CPU (‘Host’) FPGA Operator Pipelines Operator Pipelines IBM POWER CAPI + SNAP Xilinx Vivado

Operator Pipelines

AXI Stream Switch C++ API

Hybrid File System

Data Sources and Sinks Block Mapper Filesystem Metadata Store

SLIDE 12

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Users can mount Metal FS as a Linux file system

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Implemented in user space

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Example:

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Metal FS FUSE Filesystem

$ cp ~/orders.tbl /metal_fs/files/

SLIDE 13

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Metal FS Symbolic Executables

File System Driver & Pipeline Orchestrator Process change_case encrypt decrypt

Message flow via UNIX Socket Data flow via Memory-Mapped Files $ echo "Hello World" \ | /metal_fs/operators/change_case \ | /metal_fs/operators/encrypt \ | /metal_fs/operators/decrypt

SLIDE 14

Foundations

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Metal FS: Architecture Overview

CPU (‘Host’) FPGA Operator Pipelines Operator Pipelines IBM POWER CAPI + SNAP Xilinx Vivado

Operator Pipelines

AXI Stream Switch C++ API

Hybrid File System

Data Sources and Sinks Block Mapper Filesystem Metadata Store

User Interface & Instrumentation

Linux Filesystem Driver Symbolic Executables AXI Performance Monitor

SLIDE 15

Demo

SLIDE 16

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Demo Screencast

SLIDE 17

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Steps:

1.

git clone https://github.com/rs22/metalfs-workshop

2.

Start the development container by using the start script:

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start_linux, start_osx, start_win.bat

3.

Build a simulation image

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make model

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Hands-On: Prepare the Metal FS Simulation

SLIDE 18

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HLS translates the mtl_stream references into AXI Stream interfaces

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We require the keep and last signals which are optional channels in the AXI Stream protocol

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Anatomy of an Operator in Vivado HLS

struct mtl_stream_element { ap_uint<64> data; ap_uint<8> keep; ap_uint<1> last; }; void my_operator(mtl_stream &in, mtl_stream &out) { mtl_stream_element element; do { element = in.read();

ut.write(element);

} while (!element.last); }

SLIDE 19

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HLS offers the ap_uint types for integers with arbitrary bit precision

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snapu{8, 16, 32, 64}_t are typedefs for ap_uint<>

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Access bit ranges of an ap_uint like this (similar to VHDL):

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Concatenate integers:

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Programming with HLS: Arbitrary-Precision integers

snapu16_t my_integer; snapu8_t high_byte = my_integer(15, 8); snapu8_t high_byte = 0xFF; snapu8_t low_byte = 0x0A; snapu16_t both_bytes = (high_byte, low_byte);

SLIDE 20

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Steps:

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Build a new model

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make model

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Start the simulation

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make sim

3.

In the simulation window:

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snap_maint

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metal_fs /mnt

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Start a second shell in the container using the start script

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cat src/hls_operator_colorfilter/apples_simulation.bmp \ | /mnt/operators/colorfilter \ > out.bmp

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Hands-On: Run the Metal FS Simulation

SLIDE 21

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Goal: Implement an operator that processes a bitmap image and converts it to grayscale, except for pixels where red is the dominant color

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Operator is prepared in src/hls_operator_colorfilter/hls_operator_colorfilter.cpp

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Bitmap header is not aligned to a stream word boundary

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The template temporarily inserts a padding to make processing easier

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Task 1: Exclude the bitmap header data from being transformed

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Task 2: Leave those pixels unmodified where red is the dominant color

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The operator code can be compiled into software, useful for testing

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src/hls_operator_colorfilter $ make test

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Hands-On: Implement a Grayscale Filter operator

SLIDE 22

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Try out your implementation in the simulation environment

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Profiling results look like this:

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Hands-On: Simulating the Operator Implementation

Shell 1: $ make model $ make sim Simulation Shell: $ snap_maint $ metal_fs /mnt Shell 2: # -p enables profiling $ cat src/hls_operator_colorfilter/apples_simulation.bmp \ | /mnt/operators/colorfilter -p \ > out.bmp

STREAM BYTES TRANSFERRED ACTIVE CYCLES DATA WAIT CONSUMER WAIT TOTAL CYCLES MB/s input 6538 818 21% 634 16% 2439 63% 3897 419.43

utput 6538 818 21% 3076 79% 0 0% 3897 419.43

Our operator limits the pipeline throughput

SLIDE 23

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Open the xsim GUI

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xsim –gui $SNAP_ROOT/hardware/sim/xsim/latest/top.wdb &

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Only every four cycles a new stream element is processed

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Hands-On: Inspecting the Simulation Waveform

4 cycles read write

SLIDE 24

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Open the colorfilter operator project in Vivado HLS

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vivado_hls &

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Project: src/hls_operator_colorfilter/hls_operator_colorfilter_sln_[…]

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Switch to Analysis View

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Hands-On: Vivado HLS Analysis View

Inner processing loop has four steps and is not pipelined

SLIDE 25

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Add a HLS PIPELINE pragma inside the do-while loop

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New Performance Profile:

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Profiling Results:

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Hands-On: Vivado HLS Pipeline pragma

STREAM BYTES TRANSFERRED ACTIVE CYCLES DATA WAIT CONSUMER WAIT TOTAL CYCLES MB/s input 6538 818 55% 668 45% 0 0% 1489 1097.72

utput 6538 818 55% 668 45% 0 0% 1489 1097.72

SLIDE 26