SOC Laboratory Course in NCTU Trial Run Report Speaker: Kun-Bin - - PowerPoint PPT Presentation

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SOC Laboratory Course in NCTU Trial Run Report Speaker: Kun-Bin - - PowerPoint PPT Presentation

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SOC Laboratory Course in NCTU Trial Run Report Speaker: Kun-Bin Lee Directed by Prof. Chein-Wei Jen Department of Electronics Engineering National Chiao Tung University {kblee, cwjen}@twins.ee.nctu.edu.tw Jul. 15, 2003 Lab Modules of

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SOC Laboratory Course in NCTU – Trial Run Report

Speaker: Kun-Bin Lee Directed by Prof. Chein-Wei Jen

Department of Electronics Engineering National Chiao Tung University {kblee, cwjen}@twins.ee.nctu.edu.tw

  • Jul. 15, 2003
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Institute of Electronics, National Chiao Tung University SOC Laboratory Course in NCTU – Trial Run Report

Lab Modules of SOC Laboratory (1/2)

  • 0. SOC Overview and ARM Integrator: ARM architecture, ARM-based

SOC and Development tools

  • 1. Code Development: Compiler, Assembler, Linker, and ARM/Thumb

Code Inter-working

  • 2. Debugging and Evaluation: Debugging, Single-step, and Breakpoint,

Instruction Simulator (ARMulator), Cycle Count, Timing Measurement, Profiler, and User’s Models

  • 3. Core Peripherals: Software Modeling for Interrupt Controller,

Counter/Timer, Reset, and Pause Controller

  • 4. Real-Time OS: Driver, Function Kernels, Scheduler, API, and

Communication/Memory Management

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Institute of Electronics, National Chiao Tung University SOC Laboratory Course in NCTU – Trial Run Report

Lab Modules of SOC Laboratory (2/2)

  • 5. On-chip Bus: AHB, APB, Bus Bridge, Arbiter, and VCI Interface
  • 6. Memory Controller: On-chip SRAM, DMA Controller, and External

Memory Interface

  • 7. ASIC Logic: Acceleration Building Blocks, FPGA Designs and

Design Reuse, Generator/Configuration

  • 8. Standard I/O: GPIO, UART, USB, 1394, Keyboard, Mouse,

Button/Switch, Touch screen, and Sensor

  • 9. JTAG and Multi-ICE: Test Access and System Debugging

10.Case Design for Term project:JPEG2000, MPEG2, xDSL, IEEE 802.11x, or Bluetooth

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Institute of Electronics, National Chiao Tung University SOC Laboratory Course in NCTU – Trial Run Report

Process of the Lab Course

  • Affiliate with the course: IP Core Design

– http://twins.ee.nctu.edu.tw/courses/ip_core_01/index.html 2001.9~2002.1 39 students, 5 TAs – http://twins.ee.nctu.edu.tw/courses/ip_core_02/index.html 2001.9~2002.1 41 students (exclude 7 withdrawers), 4 TAs

  • Lab schedule

– Four labs/assignments every two weeks – Pick one application and go through the assignments – Final exam is affiliated to IP Core Design

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Institute of Electronics, National Chiao Tung University SOC Laboratory Course in NCTU – Trial Run Report

Lab Organization in NCTU

Getting Start with ADS Working with AXD Software Quality Measurement ARM Integrator Environment µC/OS-II

Virtual Prototyping Profiling Application Digital IP Authoring RTOS µHAL Driver Rapid Prototyping Embedded SW Authoring

Coding Guideline Coverage-Driven Verification

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Institute of Electronics, National Chiao Tung University SOC Laboratory Course in NCTU – Trial Run Report

Code Development

  • Goal

– How to create an application using ARM Developer Suite (ADS) – How to change between ARM state and Thumb state when writing code for different instruction sets

  • Principles

– Processor’s organization – ARM/Thumb Procedure Call Standard (ATPCS)

  • Guidance

– Flow diagram of this Lab – Preconfigured project stationery files

  • Steps

– Basic software development (tool chain) flow – ARM/Thumb Interworking

  • Requirements and

Exercises

– See next slide

  • Discussion

– The advantages and disadvantages of ARM and Thumb instruction sets.

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Institute of Electronics, National Chiao Tung University SOC Laboratory Course in NCTU – Trial Run Report

Code Development (cont’)

  • ARM/Thumb Interworking

– Exercise 1: C/C++ for “Hello” program

  • Caller: Thumb
  • Callee: ARM

– Exercise 2: Assembly for “SWAP” program, w/wo veneers

  • Caller: Thumb
  • Callee: ARM

– Exercise 3: Mixed language for “SWAP” program, ATPCS for parameters passing

  • Caller: Thumb in Assembly
  • Callee: ARM in C/C++
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Institute of Electronics, National Chiao Tung University SOC Laboratory Course in NCTU – Trial Run Report

Debugging and Evaluation

  • Goal

– A variety of debugging tasks and software quality evaluation

  • Debugging skills

– Set breakpoints and watchpoints – Locate, examine and change the contents of variables, registers and memory

  • Skills to evaluate software quality:

– Memory requirement of the program – Profiling: Build up a picture of the percentage of time spent in each procedure. – Evaluate software performance prior to implement on hardware

– Thought in this Lab the debugger target is ARMulator, but the skills can be applied to Multi-ICE/Angel with the ARM development board(s). – The instructions are based on the Dhrystone test software

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Institute of Electronics, National Chiao Tung University SOC Laboratory Course in NCTU – Trial Run Report

Debugging and Evaluation

  • Requirements and Exercises

– Optimize 8x8 inverse discrete cosine transform (IDCT) [1] according to ARM’s architecture. – Deliverables

  • Discussion

– Explain the approaches you apply to minimize the code size and enhance the performance of the lotto program according to ARM’s architecture. – Select or modify the algorithms

  • f the code segments used in

your program to fit to ARM's architecture. – SIMD operations in ARM core

  • Principles

– The Dhrystone Benchmark – CPU’s organization

  • Guidance

– Steps only

  • Steps

– Debugging skills – Memory requirement and Profiling – Virtual prototyping – Efficient C programming

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Institute of Electronics, National Chiao Tung University SOC Laboratory Course in NCTU – Trial Run Report

In ARM CPU

AMBA Data AMBA Interface

  • Inst. & data

Virtual Address JTAG and non-AMBA signals

  • Inst. & data cache

CP15 MMU

ARM Core

EmbeddedICE & JTAG Write Buffer

Physical Address AMBA Address

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Institute of Electronics, National Chiao Tung University SOC Laboratory Course in NCTU – Trial Run Report

Software Quality Measurement

  • Memory Requirement

– Data type: Volatile (RAM), non-volatile (ROM) – Memory performance: access speed, data width, size and range

  • Performance Benchmarking

– Harvard Core

  • D-cycles, ID-cycles, I-cycles

– von Newman Cores

  • N-cycles, S-cycles, I-Cycles, C-Cycles

– Clock rate

  • Processor, external bus

– Cache efficiency

  • Average memory access time = hit time +Miss rate x Miss Penalty
  • Cache Efficiency = Core-Cycles / Total Bus Cycles
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Institute of Electronics, National Chiao Tung University SOC Laboratory Course in NCTU – Trial Run Report

Virtual Prototyping

  • Features

– Trade-off by modifying system parameters & checking results – Develop & test device drivers – Test the correctness of compiler generated code – Visualize behavior of system and peripherals – Test the correctness of application algorithms

CPU ISS CPU Debugger (GUI) CPU ICE UART Model Intr cntrl Model Parallel I/O Model Timer Model Memory Model Rapid Prototype USB Model Codec Model BLC Model

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Institute of Electronics, National Chiao Tung University SOC Laboratory Course in NCTU – Trial Run Report

Virtual Prototyping Environment

ARMulator startup banner : System Output Monitor - RDI Log Default MCCFG = 3

ARMulator ADS1.1 [Build 709] ARM940T, 4kB I-cache, 4kB D-cache, 10.00MHz core clock, (Physical memory, 3.3MHz, 4GB), Little endian, Debug Comms Channel, Mapfile, Timer, Tube, Profiler, Pagetables, IntCtrl, Tracer, Millisecond [3333.33 cycles_per_millisecond], Semihost ARM RDI 1.5.1 -> ASYNC RDI Protocol Converter ADS v1.1 Memory map: 00000000..7fffffff, 32-Bit, wr, wait states: RN=0 WN=0 RS=0 WS=0 RIS=0 WIS=0 ARMulator ADS1.2 [Build 805] ARM940T, 4KB I-cache, 4KB D-cache, 200.00MHz FCLK, (Physical memory, BIU), Little endian, Semihosting, Debug Comms Channel, 66.7MHz, 4GB, Mapfile, Timer, Profiler, Tube, Millisecond [66666.7 cycles_per_millisecond], Pagetables, IntCtrl, Tracer, RDI Code sequences ARM RDI 1.5.1 -> ASYNC RDI Protocol Converter ADS v1.2 [Build number 805].

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Institute of Electronics, National Chiao Tung University SOC Laboratory Course in NCTU – Trial Run Report

Core Peripherals

  • Goal

– Understand the HW/SW coordination

  • Memory-mapped device
  • Operation mechanism of

polling and Timer/Interrupt

  • HAL

– Understand available resource

  • f ARM Integrator
  • semihosting
  • Principles

– Semihosting – Interrupt handler – Architecture of Timer and Interrupter controller

  • Guidance

– Introduction to Important functions used in interrupt handler

  • Steps

– The same to that of code development

  • Requirements and

Exercises

– Use timer to count the total data transfer time of several data references to SSRAM and SDRAM.

  • Discussion

– Compare the performance between using SSRAM and SDRAM.

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Institute of Electronics, National Chiao Tung University SOC Laboratory Course in NCTU – Trial Run Report

Lint and Coding Guideline

  • Syntax and semantic checks that ensure compliance with

VHDL (IEEE 1076-1993) and Verilog (IEEE 1364/OVI 1.0, 2.0) HDL language standards

  • Coding checks that analyze the HDL for simulation,

synthesizability, design-for-reuse, and test requirements

  • Design practice checks that include hierarchy,

combinatorial loops, reset/clocking styles and many more

  • Style, documentation, and naming checks that ensure

adherence to coding guidelines

  • In this Lab: VN-Check from TransEDA Verification

Navigator

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Institute of Electronics, National Chiao Tung University SOC Laboratory Course in NCTU – Trial Run Report

Coverage-Driven Verification

  • Quantitatively analyze the simulation

completeness with well-defined coverage metrics

– Although 100% coverage still cannot guarantee a 100% error-free design

  • Generate more patterns for the uncovered areas

using formal techniques or designers’ knowledge

  • Tests optimization by eliminating tests that do not

add new coverage

  • Prioritize tests for regression runs
  • Provide a more systematic way to manage the

verification process

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Institute of Electronics, National Chiao Tung University SOC Laboratory Course in NCTU – Trial Run Report

Real-Time OS

  • Goal

– A guide to use RTOS and port programs to it

  • Principles

– Basic concepts and capabilities of RTOS

  • Task, task scheduling &

context switch

  • Resource management using

Semaphore

  • Inter-process communication

using Mailbox

  • Memory management

– Coding guideline for a program running on the embedded RTOS – Setting up the ARMulator

  • Guidance
  • Steps

– Building µC/OS-II – Building Program with µC/OS-II – Porting Program to µC/OS-II

  • Requirements and

Exercises

– Write an embedded software for ID checking engine and a front–end interface

  • Discussion

– What are the advantages and disadvantages of using RTOS in SoC design?

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Institute of Electronics, National Chiao Tung University SOC Laboratory Course in NCTU – Trial Run Report

ASIC Logic

  • Goal

– HW/SW Co-verification using Rapid Prototyping

  • Principles

– Basics and work flow for prototyping with ARM Integrator – Target platform: AMBA AHB sub-system

  • Guidance

– Overview of examples used in the Steps

  • Steps

– Understand the files for the example designs and FPGA tool – Steps for synthesis with Xilinx Foundation 3.1i

  • Requirements and Exercises

– RGB-to-YUV converting hardware module

  • Discussion

– In example 1, explain the differences between the Flash version and the FPGA one. – In example 1, explain how to move data from DRAM to registers in MYIP and how program access these registers. – In example2, draw the interconnect among the functional units and explain the relationships

  • f those interconnect and

functional units in AHB sub-system – Compare the differences of polling and interrupt mechanism

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Institute of Electronics, National Chiao Tung University SOC Laboratory Course in NCTU – Trial Run Report

Most Students Failed in

  • Interrupt handling
  • AMBA compliance

– Transaction-based verification with coverage analysis – Synopsys AMBA VIP / ACT

Driver BFM DUT Response BFM Test Program Monitor Monitor

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Institute of Electronics, National Chiao Tung University SOC Laboratory Course in NCTU – Trial Run Report

Others Issues

  • Memory management

– Heap/Stack setting

  • FPGA tool usage
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Institute of Electronics, National Chiao Tung University SOC Laboratory Course in NCTU – Trial Run Report

How to Improve the Effectiveness of the Course ?

  • Prerequisites notification

– Cell-based VLSI design – C

  • Computer-based test and/or oral test
  • Terse materials
  • Training the lecturers and TAs
  • Detailed reference information
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Institute of Electronics, National Chiao Tung University SOC Laboratory Course in NCTU – Trial Run Report

Summary

  • Seam the holes in and the gaps between the lab

modules

– Interrupt – Bus interface – …

  • The ways to deliver course materials and

knowledge to students

– Organize the materials such that the lab modules can be taught in a great many ways