Introduction to the x86 Architecture Camiel Vanderhoeven September - - PowerPoint PPT Presentation

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Introduction to the x86 Architecture Camiel Vanderhoeven September - - PowerPoint PPT Presentation

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Introduction to the x86 Architecture Camiel Vanderhoeven September 29, 2015 Introduction to the x86 Architecture This information contains forward looking statements and is provided solely for your convenience. While the information herein

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SLIDE 1

Introduction to the x86 Architecture

September 29, 2015

Camiel Vanderhoeven

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SLIDE 2

Introduction to the x86 Architecture

This information contains forward looking statements and is provided solely for your convenience. While the information herein is based on our current best estimates, such information is subject to change without notice.

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SLIDE 3

x86 Heritage Comparison at a Glance CPU Design Strategy Register Set Instruction Encoding Memory Layout VMS RAS Features Proliferation of x86

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SLIDE 4

x86 Development Timeline

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SLIDE 5

New Designs vs Extensions

32- bit VAX 64-bit Alpha 64-bit Itanium 16-bit 8086 286 PM 32-bit i386 AMD 64- bit

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SLIDE 6

Nomenclature

Architecture Sub-arch. First in Other implementations x86 (16-bit) 8086 8086 8088, V20, V30, 80186 i286 80286 IA-32 (32-bit) i386 80386 Am386 i486 80486 Am486 i586 Pentium Pentium MMX, K5, K6 i686 Pentium Pro Pentium II, Pentium III, Pentium 4, Athlon x86-64 (64-bit) AMD64 Opteron Athlon 64, Turion, Sempron, Phenom Intel 64 Xeon Pentium 4 “F”, Celeron, Core

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SLIDE 7

x64

Confusion

AMD64 x86-64

Intel64 IA-32e EM64T iAMD64

AMD Intel Others (Microsoft, Sun, UEFI) Joke

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SLIDE 8

x64

Confusion

AMD64 X86-64

Intel64 IA-32e EM64T iAMD64

AMD Intel Others (Microsoft, Sun, UEFI) Joke

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SLIDE 9

Chip brand names and generations

  • Intel64 brands

− Xeon − Core − Pentium − Celeron − Atom − Quark

  • AMD64 brands

− Opteron − Athlon − Sempron − FX − A-Series

  • Intel64 microarchitectures

− Core, Penryn − Nehalem, Westmere − Sandy Bridge, Ivy Bridge − Haswell, Broadwell − Skylake

  • AMD64 microarchitectures

− K8 Hammer, K10, Fusion − Bobcat, Jaguar, Puma − Bulldozer, Piledriver, Steamroller, Excavator − Zen

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SLIDE 10

ISA Extensions

Name First in Function x87 8086+8087 (1980) Floating Point Co-processor PM 80286 (1982) Protected Mode: Virtual Memory IA-32 80386 (1985) 32-bit PAE Pentium Pro (1995) Physical Address Extension MMX Pentium MMX (1997) MultiMedia Extension (Integer SIMD) 3Dnow! AMD K6-2 (1998) 3D Graphics (Floating Point SIMD) SSE(n) Pentium III (1999) Streaming SIMD Extensions (FP SIMD) x86-64 Opteron (2003) 64-bit VT-x Pentium 4 (2005) Virtualization support AMD-V Athlon 64 (2006) Virtualization support AES-NI Westmere (2010) Advanced Encryption Standard AVX(n) Sandy Bridge (2011) Advanced Vector Extensions (FP SIMD) TSX Haswell (2013) Transactional Synchronization Extension MPX Skylake (2015) Memory Protection Extensions

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SLIDE 11

x86 Heritage Comparison at a Glance CPU Design Strategy Register Set Instruction Encoding Memory Layout VMS RAS Features Proliferation of x86

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SLIDE 12

Some Numbers

VAX Alpha Itanium2 x86 Word size 32 64 64 64 Architecture CISC RISC EPIC CISC* Manufacturer DEC DEC Intel Intel AMD VIA GP Registers 16 32+32(FP) 128+128(FP) 16+8(MMX)+16(XMM) Orthogonality YES YES

  • Instructions

~460 ~135 ~150 >600**

  • Addr. Modes

24 4 6 10

  • Instr. size

8-400 bits 32 bits 41b (3/128b) 8-120 bits transistors 1.3M (NVAX) 130M (EV7) 3.1B (Poulson***) 5.6B (E7-v3****) * With an underlying RISC-Like core ** Depending on how you count them *** 8 cores **** 15 cores

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SLIDE 13

x86 Heritage Comparison at a Glance CPU Design Strategy Register Set Instruction Encoding Memory Layout VMS RAS Features Proliferation of x86

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SLIDE 14

Traditional CISC Architecture (VAX)

  • Complex Instruction Set Computer
  • Complex instructions, mixing computation and

memory access

  • Microcoded implementations
  • Makes optimizing code execution by the

processor difficult

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RISC Architecture (Alpha)

  • Reduced Instruction Set Computer
  • Simple instructions, separating computation and

memory access

  • Hardwired
  • Relatively easily optimized by processor (parallel

execution, re-ordering, pipelining, branch prediction, but…

  • Optimization hardware becoming increasingly

complex

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SLIDE 16

EPIC Architecture (Itanium)

  • Explicitly Parallel Instruction Set Computer
  • Simple instructions, separating computation and

memory access

  • Parallel execution of instruction groups,

separated by compiler-inserted stops.

  • Predication instead of conditional branching
  • Mostly hardwired
  • Burden of optimization shifted to compiler (though

Poulson fixes that by doing some reordering)

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SLIDE 17

Modern CISC Architecture (x86)

  • Complex instructions are translated into RISC-like

micro-ops

  • Partly hardwired
  • Extensive optimization performed by processor

(parallel execution, re-ordering, pipelining, branch prediction) after translation to micro-ops

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SLIDE 18

x86 Heritage Comparison at a Glance CPU Design Strategy Register Set Instruction Encoding Memory Layout VMS RAS Features Proliferation of x86

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SLIDE 19

VAX Register Set

R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 AP/R12 FP/R13 SP/R14 PC/R15 PSL IPR’s

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Alpha Register Set

R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 PC PS IPR’s R16 R17 R18 R19 R20 R21 R22 R23 R24 AI/R25 RA/R26 PV/R27 R28 FP/R29 SP/R30 RZ/R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31

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Itanium Register Set

RZ/GR0 GR1 GR2 GR3 GR4 GR5 GR6 GR7 GR8 GR9 GR10 GR11 GR12 GR13 GR14 GR15 IP UM IPR’s GR16 GR17 GR18 GR19 GR20 GR21 GR22 GR23 GR24 GR25 GR26 GR27 GR28 GR29 GR30 GR31 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 FR127 GR32-GR127

  • Reg. Stack

FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 Pr127 Pr0 Pr1 Pr2 Pr3 Pr4 Pr5 Pr6 Pr7 Pr8 Pr9 Pr10 Pr11 Pr12 Pr13 Pr14 Pr15 BR0 BR1 BR2 BR3 BR4 BR5 BR6 BR7

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SLIDE 22

x86 Register Set

RAX RCX RDX RBX RSP RBP RSI RDI R8 R9 R10 R11 R12 R13 R14 R15 RIP RFLAGS IPR’s MMX0/FPR0 MMX1/FPR1 MMX2/FPR2 MMX3/FPR3 MMX4/FPR4 MMX5/FPR5 MMX6/FPR6 MMX7/FPR7 XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 XMM9 XMM10 XMM11 XMM12 XMM13 XMM15 XMM16

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SLIDE 23

x86 register Part naming

RAX AL AH AX EAX

63 31 15 7

R8 R8B R8W R8D

63 31 15 7

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SLIDE 24

x86 Heritage Comparison at a Glance CPU Design Strategy Register Set Instruction Encoding Memory Layout VMS RAS Features Proliferation of x86

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VAX Instruction encoding

Opcode

1 or 2 bytes, 1

  • pcode per
  • peration

[Operand 1]

1 byte containing addressing mode and register number, up to 4 bytes of displacement, immediate data,

  • r address

[Operand 2 … n]

same

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SLIDE 26

Alpha Instruction Encoding

Opcode

6 bits, one

  • pcode per
  • peration

Operands

26 bits, encoding up to 3 registers, up to 21-bit displacement, 8- bit literal value, up to 16-bit function specifier

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SLIDE 27

Itanium Instruction Encoding

Syllable 41 bits

Opcode 4 bits Operands 31 bits, typically 10-bit function and 3 registers Predicate 6 bits

Syll.

Opcode Operands Predicate

Syll.

Opcode Operands Predicate

Template 5 bits

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SLIDE 28

Intel x86 Instruction Encoding

[Prefixes]

1-6 bytes specifying address and operand size

  • verride, extended

register set, extended instruction set, locking, repetition, segment, branch hints

Opcode

1-3 bytes Multiple opcodes per operation

[Mod-R/M]

1 byte specifying addressing mode and either 2 registers or 1 register + 3 bits

  • pcode extension

[SIB]

1 byte specifying scale factor, index and base registers for indexed addressing

[Displacement]

1-8 bytes specifying a displacement or

  • ffset

[Immediate]

1-8 bytes specifying an immediate value

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x86 Heritage Comparison at a Glance CPU Design Strategy Register Set Instruction Encoding Memory Layout VMS RAS Features Proliferation of x86

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Memory Specs

VAX Alpha Itanium x86 Address size 32 64 64 64 Page size 512 8K/64K/512K/4M 4K-4G 4K/2M/1G Split VA Space no yes yes yes PT Levels 2 3 3 4 PTE Cache no no VHPT PDE cache

  • Virt. Addr. Size

32 48 54 48

  • Phys. Addr. Size 32

44 50 52 (48) Segmentation no no no yes (kind of)

  • Prot. Bits in TLB 4 enc[KESU][RW] 11 [KESU][RW],

FO[RWE] 7 enc[KESU], enc[RWX] 3 R/W, U/S, XD

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x86 Heritage Comparison at a Glance CPU Design Strategy Register Set Instruction Encoding Memory Layout VMS RAS Features Proliferation of x86

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SLIDE 32

Hardware/Software Boundaries

OS CPU Console QUEUE etc.

VAX

OS CPU QUEUE etc. Console

MicroVAX

OS CPU SRM PALCODE

Alpha

OS CPU UEFI SWIS

Itanium and x86-64

Hardware Firmware OS

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x86 Heritage Comparison at a Glance CPU Design Strategy Register Set Instruction Encoding Memory Layout VMS RAS Features Proliferation of x86

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RAS Features in Itanium and Xeon

Feature Itanium Xeon Cache ECC Coverage ✓ ✓ Single-bit Memory Error Correction ✓ ✓ Double-bit Memory Error Detection & Retry ✓ ✓ ECC on Data Bus ✓ ✓ Internal Logic Soft Error Checking ✓ Skylake-EX Bad Data Containment ✓ ✓ Intel Cache Safe ✓ ✓ Memory Sparing ✓ ✓ Memory Mirroring ✓ ✓ Hot-Plug I/O ✓ ✓ Memory Hot-Swap ✓ ✓ Processor Lock-Step ✓ ✓

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x86 Heritage Comparison at a Glance CPU Design Strategy Register Set Instruction Encoding Memory Layout VMS RAS Features Proliferation of x86

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SLIDE 36

Lifespans of different architectures

1974 1979 1984 1989 1994 1999 2004 2009 2014 POWER MIPS SPARC X86 Itanium Alpha VAX Pre Dev Life VMS Sales Post

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2013 Server Market

Revenue

X86 (30.7B) Itanium (1B) RISC (4.8B) Other (5.6B)

Units

X86 (9.8M) Itanium (21K) RISC (90K) Other (10K)

100 200 300 400 500 600

K$/Unit

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SLIDE 38

For more information, please contact us at:

RnD@vmssoftware.com

VMS Software, Inc. • 580 Main Street • Bolton MA 01740 • +1 978 451 0110