Luis Garcia, Andres Cicuttin, Maria Liz Crespo, Kasun Sameera - - PowerPoint PPT Presentation

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Luis Garcia, Andres Cicuttin, Maria Liz Crespo, Kasun Sameera - - PowerPoint PPT Presentation

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Desig sign for r Port rtabil ilit ity of f Reconfig igurable le In Instrumentatio ion Base sed on Programmable le Systems-on on-Chip ip Luis Garcia, Andres Cicuttin, Maria Liz Crespo, Kasun Sameera Manatunga, (ICTP,Italy) Rodrigo

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Desig

sign for r Port rtabil ilit ity of f Reconfig igurable le In Instrumentatio ion Base sed on Programmable le Systems-on

  • n-Chip

ip

Andres Cicuttin ICTP – MLAB Multidisciplinary Laboratory of The Abdus Salam International Centre for Theoretical Physics Trieste, Italy

  • A. Cicuttin, ICTP. SPL2019

1 Luis Garcia, Andres Cicuttin, Maria Liz Crespo, Kasun Sameera Manatunga, (ICTP,Italy) Rodrigo Melo, Bruno Valinotti, (INTI, Argentina) Stefano Levorato (INFN, Italy)

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Emulated Instruments Virtual Instrument Reconfigurable Instrument

Reconfigurable Virtual Instrumentation

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Reconfigurable Virtual Instrumentation

Transient recorder Function generator Oscilloscope Multimeter Spectrum Analyzer

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Hardware modularity and porting across different platforms

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Portability among different FMC Carriers of instrumentation based on dedicated hardware modules

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FMC carriers FMC modules

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Port 1 controller

* * *

Port 2 controller Port M controller

* * *

External Hardware Controller N External Hardware Controller 2 External Hardware Controller 1

  • A. Cicuttin, ICTP. SPL2019

A poss ssible FPGA Glo lobal Architecture for r RVI

Dual Port Memory FIFO IN FIFO OUT Registers

PC Communication block

PC  FPGA communication

* * *

Instrument N Core Instrument 2 Core Instrument 1 Core External Memory Controller RVI Bus

High Speed Connections

Status Instructions Parameters

RVI CONTROLLER

With DMA capabilities Miscellaneous and Debugging Facilities Controller

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RICH-1

DOLINA PC de Control del RICH (Ethernet) 8 Redes TDM de DSP BORA-0 BORA-11 BORA-12 BORA-23 Fibra desde TCS Pixel (0,0) Pixel (287, 287) 24 192 tarjetas BORA Fibras Opticas Cámara Fibras Opticas Cámara 7 Cámara 6 Cámara 5 Cámara 4 Cámara 3 Cámara 2 Cámara 1 Cámara 0 PCI

Global Architecture of a distributed instrumentation

  • A. Cicuttin, ICTP. SPL2019

DAQ System Ring Imaging Cherenkov Detector COMPASS Experiment CERN, 2004. Pixels : ~ 80000 Ave trigger rate: ~ 100KHz Dead time: ~ 1 us Max data rate: ~ 100GB/s 8

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Dolina, Side B

Dolina, Side A Da Data movement th through dis istr trib ibuted in instr trumentation

TDP RAMs uP PCI Bus FIFOs FPGA DSPs

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Reconfigurable Instrumentation based on SoC FPGA Global Architecture

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SoC FPGA Time Critical External Hardware FPGA uP PC FPGA-uP communication block Non Time Critical External Hardware External Memory Middleware Ext HW Controllers

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Native or Wishbone interface

FPGA2uP FIFOs uP2FPGA FIFOs True Dual Port RAM Memory Mapped AXI Lite/ AXI Full/ AXI Stream

FPGA

External Hardware Interface Native or Wishbone interface User Core Logic Design Registers

External DDR RAM Memory Controller

uP

Control Registers/ FIFOs and True Dual Port RAM FPGA – uP Communication SW (uP) uP–PC Communication SW

User Core Program

Reconfigurable Virtual Instrumentation Based on a single SoC FPGA Typical Global Architecture

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uP – PC Communication SW (uP) Virtual consoles & Control Computing

PC

FMC Connector External Hardware (Application specific) Input/outp ut signals External RAM Memory Controller External RAM Memory Controller

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Native or Wishbone interface FIFOs FPGA2Rout FIFOs Rout2FPGA

FPGA

Registers True Dual Port RAM Reserved area Reserved area UDMA controller

CommBlock

Native or Wishbone interface

FPGA  FPGA

Native or Wishbone interface FIFOs FPGA2uP FIFOs uP2FPGA Memory Mapped AXI Lite / Full / Stream

FPGA

Registers True Dual Port RAM Reserved area Reserved area

uP

UDMA controller

CommBlock

FPGA  uP

Router Flags/semaphores for logic protocols DMA instructions Payload data Standardized Data Packets

Reconfigurable Distributed Instrumentation Based on multiple SoC FPGA

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A block view of the Communication Block and memory mapping of the CB ports

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ComBlock: : Memory mapping on the uP side, and its connections with functional blocks implemented in the FPGA.

SoC Bus WB or Native interfaces

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Asynchronous timing diagram of a flags-based protocol for safe data transmission through the TDPRAM of the CB

A possible logical utilization of reserved registers for safe data transfer through TDP RAM

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uP-Subsystem

AXI Bus Custom connections with the FPGA-subsystem

Top level schematic: ComBlock and its connections

ComBlock

FPGA-Subsystem

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AXI Bus

Custom connections with the FPGA-subsystem

To external HW uP Subsystem FPGA subsystem ComBlock

Top level schematic: ComBlock and its connections

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Configuration wizard window for the ComBlock

(Vivado System Edition)

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Communication between the FPGA and uP subsystems

  • 1. Physical

Allows a simple utilization of the resources of the CB as storage elements.

  • 2. Logical

Includes a basic asynchronous logic protocol for a safe utilization of the ComBlock. It requires some reserved areas in the TDPRAM and some reserved registers.

  • 3. Systemic

Implements a high level protocol based on a set of complex instructions for Direct Memory Access (DMA). It provides transparent access from any domain to all resources mapped in a global memory mapping, including those that are not immediately accessible but that are directly accessible from the other domain. It requires a DMA machine in the FPGA, and a corresponding software routine in the uP. Each level corresponds to a communication layer. Each layer relays on the services offered by the immediate layer below, and provides services that can be used by the layer immediately above.

It can be implemented by mean of three different hierarchical levels:

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Resource utilization of the CB in different Devices

Family Name Slice LUTs Slice Registers F7 Muxes F8 Muxes Block RAM (kBytes) Zynq-7000 xc7z020 726

816 128 64 290.25

Spartan-7 xc7s100 726

816 128 64 290.25

Artix-7

xc7a200 726 816 128 64 290.25

Kintex UltraScale+ xcku15p 854

816 128 64 290.25

Virtex UltraScale+ xcvu13p 854

816 128 64 290.25

  • RESOURCE UTILIZATION OF THE CB IN XILINXFPGAS

Family Name ALMs Logic Registers Block RAM (kBytes) Cyclone V 5CSEMA5F31C6 764 563 290.25 Cyclone 10 LP 10CL006YU256A7G 1170 559 290.25

Cyclone IV GX

EP4CGX15BF14A7 1171 559 290.25

Cyclone IV E

EP4CE6E22A7 1170 559 290.25

  • RESOURCE UTILIZATION OF THE CB IN ALTERA FPGAS
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Resource usage of a high-speed data acquisition system without and with the communication block

Name Without Communication Block With Communication Block FPGA_ Subsystem uP_ Subsystem Others Total FPGA_ Subsystem uP_ Subsystem Communication _Block Total Slice LUTs 187 960 6691 7838 (14.73%) 186 1466 834 2486 (4.67%) Slice Registers 264 1244 12696 14204 (13.35%) 264 1957 884 3105 (2.92%) F7 Muxes 62 62 (0.23%) 62 128 190 (0.71%) F8 Muxes 0 (0%) 64 64 (0.48%) Block RAM Tile 66.5 66.5 (47.5%) 65 65 (46.43%)

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Conclusions

1. The proposed Communication Block is a general purpose and reusable IP which completely absorbs the complexities of the SoC Interconnection Bus in modern SoC FPGA devices. 2. FPGA and uP subsystems can efficiently communicate through a ComBlock without any significant loss in performance and without any penalty in resources utilization. 3. Migration of complex systems among different SoC FPGA families and vendors is easier when based on ComBlocks since it essentially requires the porting of the ComBlock only. 4. Most of the uP embedded software and FPGA subsystem designs can be ported with minimal effort, and with facilitated debugging and optimization. 5. Since each subsystem deals with the other subsystem by reading and writing in the memory locations of the ComBlock, this block provides an abstract view of one subsystem to the other interacting subsystem. 6. The use of a ComBlock imposes a structured design methodology by mean of an explicit separation of the work in the uP and FPGA domains. 7. The implicit ComBlock strategy could simplify concrete Hardware/Software partitioning and implementation of complex cooperative activities.

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Thank you for your attention!

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