Measurement Results of a Large Dynamic Range CSA - UMC 180 nm - - PowerPoint PPT Presentation

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Measurement Results of a Large Dynamic Range CSA - UMC 180 nm - - PowerPoint PPT Presentation

Aug 26, 2022 122 likes •346 views

Outline Architecture and Properties Mode of Operation Measured Results Summary and Outlook Measurement Results of a Large Dynamic Range CSA - UMC 180 nm Process - P. Wieczorek, H. Flemming and H. Deppe GSI Helmholtzzentrum fuer

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SLIDE 1

Outline Architecture and Properties Mode of Operation Measured Results Summary and Outlook

Measurement Results of a Large Dynamic Range CSA

  • UMC 180 nm Process -
  • P. Wieczorek, H. Flemming and H. Deppe

GSI Helmholtzzentrum fuer Schwerionenforschung GmbH Experiment Electronics Department

  • 06. November 2018
  • P. Wieczorek, H. Flemming and H. Deppe

Experiment Electronics

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SLIDE 2

Outline Architecture and Properties Mode of Operation Measured Results Summary and Outlook

Outline

1

Architecture and Properties

2

Mode of Operation

3

Measured Results

4

Summary and Outlook

  • P. Wieczorek, H. Flemming and H. Deppe

Experiment Electronics

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SLIDE 3

Outline Architecture and Properties Mode of Operation Measured Results Summary and Outlook Overview Properties

Outline

1

Architecture and Properties Overview Properties

2

Mode of Operation

3

Measured Results

4

Summary and Outlook

  • P. Wieczorek, H. Flemming and H. Deppe

Experiment Electronics

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SLIDE 4

Outline Architecture and Properties Mode of Operation Measured Results Summary and Outlook Overview Properties

C1 C2 C3 C4 R1 R2 R4 R3 CF1 CF2 CSA SE2DIF INT Buffer PO<4:1> OUT+ OUT− IN V ref C0 LOG_D CAP_reset PM<4:1> C2 = 16xC0 C3 = 64xC0 C4= 128xC0 R3 = 50 k R4 = 50 k Ω Ω Ω R2 = 50 k Ω R1 = 50 k C1 = 4xC0 C0 = 200 fF CF2 = 100 fF Capacitance set Logic Vref = 0...1.8 V CF1 = 100 fF

Charge sensitive amplifier input stage Switched feedback capacitances architecture Signal transformation: single-end to differential Analogue filter and buffer at the output

  • P. Wieczorek, H. Flemming and H. Deppe

Experiment Electronics

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SLIDE 5

Outline Architecture and Properties Mode of Operation Measured Results Summary and Outlook Overview Properties

Large dynamic range of > 105 Charge coverage: from noise level up to 45 pC Differential output voltage: 1V Active reset Automatic and manual mode to set feedback capacitances

No. Unit Area Unit C0 200 fF 220 µm2 C1 4 × C0 fF 880 µm2 C2 16 × C0 fF 3523 µm2 C3 64 × C0 fF 14080 µm2 C4 128 × C0 fF 28160 µm2

  • P. Wieczorek, H. Flemming and H. Deppe

Experiment Electronics

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SLIDE 6

Outline Architecture and Properties Mode of Operation Measured Results Summary and Outlook Feedback Logic Dynamic Capacitance Extension

Outline

1

Architecture and Properties

2

Mode of Operation Feedback Logic Dynamic Capacitance Extension

3

Measured Results

4

Summary and Outlook

  • P. Wieczorek, H. Flemming and H. Deppe

Experiment Electronics

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SLIDE 7

Outline Architecture and Properties Mode of Operation Measured Results Summary and Outlook Feedback Logic Dynamic Capacitance Extension

Signal IN PA<1> PA<2> PA<3> PA<4> Threshold 1.25 V

& & & τ τ τ

Manual mode: set fixed feedback capacitances to the amplifier

Known feedback cap. configuration Chosen dynamic range is mapped on 1V

Auto mode: dynamic extension of feedback capacitance

Each subrange is 1V Additional readout of feedback configuration is necessary

  • P. Wieczorek, H. Flemming and H. Deppe

Experiment Electronics

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SLIDE 8

Outline Architecture and Properties Mode of Operation Measured Results Summary and Outlook Feedback Logic Dynamic Capacitance Extension

Measured transient during capacitance extension to the feedback is depicted Adding capacitance keeps the amplifier from saturation (up to 42pC) But: dynamic loss of 20%

  • P. Wieczorek, H. Flemming and H. Deppe

Experiment Electronics

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SLIDE 9

Outline Architecture and Properties Mode of Operation Measured Results Summary and Outlook Dynamic Range Gain Noise

Outline

1

Architecture and Properties

2

Mode of Operation

3

Measured Results Dynamic Range Gain Noise

4

Summary and Outlook

  • P. Wieczorek, H. Flemming and H. Deppe

Experiment Electronics

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SLIDE 10

Outline Architecture and Properties Mode of Operation Measured Results Summary and Outlook Dynamic Range Gain Noise 100 1000 100 1000 10000 100000 Ouput Voltage [mV] Input Charge [fC]

A-Mode C0 A-Mode C1 A-Mode C2 A-Mode C3 A-Mode C4

100 1000 100 1000 10000 100000 Ouput Voltage [mV] Input Charge [fC]

M-Mode C0 M-Mode C1 M-Mode C2 M-Mode C3 M-Mode C4

Measured with auto mode Measured with manual mode

  • Max. measured charge: up to 42pC

Different slope for cap. C1 in auto mode

  • P. Wieczorek, H. Flemming and H. Deppe

Experiment Electronics

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Outline Architecture and Properties Mode of Operation Measured Results Summary and Outlook Dynamic Range Gain Noise

0.01 0.1 1 10 1 2 3 4 5 6 Gain mV/fC

  • No. of used Cf
  • Sim. gain values
  • Cal. gain values

Measured gain values Auto Measured gain values Manual

Simulation Measured A Measured M mV/fC mV/fC mV/fC 3.94 1.330 1.892 0.855 0.922 0.818 0.205 0.255 0.253 0.0511 0.071 0.068 0.0185 0.028 0.028

Gain for C0 capacitance is about 3x lower as expected ⇒ influence of the RC - parasitic effects Optimization in next version

  • P. Wieczorek, H. Flemming and H. Deppe

Experiment Electronics

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SLIDE 12

Outline Architecture and Properties Mode of Operation Measured Results Summary and Outlook Dynamic Range Gain Noise

Summary of the noise calculation (compare: FEE Workshop 2018 at GSI)

CT = Cgs + Cdet + Cf optimise parameter CT as small as possible ⇒ low noise contribution Cdet (detector capacitance): fixed Cgs increases with the transistor geometry ⇒ trade off between transistor width and capacitance Feedback capacitance Cf : ⇒ trade off between noise and dynamic range

Cgs=20 pF; Cdet=50 pF; Cf =1 pF .... 30 pF ⇒ CT= 71...100 pF Measured CSA noise (C0 = 200fF) is σ > 0.38 fC

  • P. Wieczorek, H. Flemming and H. Deppe

Experiment Electronics

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SLIDE 13

Outline Architecture and Properties Mode of Operation Measured Results Summary and Outlook Dynamic Range Gain Noise

Following O’Conner a figure of merit (FOM) defined as FOMPreamp = Power × τs Qmax/σQ Short peaking time of τs = 20 ns Measured noise of σQ = 0.4 fC Large dynamic range of >100 000 Present design: FOM = 2fJ (excellent result)

  • P. Wieczorek, H. Flemming and H. Deppe

Experiment Electronics

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SLIDE 14

Outline Architecture and Properties Mode of Operation Measured Results Summary and Outlook Summary Outlook Noise Calc. Backup

Outline

1

Architecture and Properties

2

Mode of Operation

3

Measured Results

4

Summary and Outlook Summary Outlook

  • P. Wieczorek, H. Flemming and H. Deppe

Experiment Electronics

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SLIDE 15

Outline Architecture and Properties Mode of Operation Measured Results Summary and Outlook Summary Outlook Noise Calc. Backup

First Prototype works excellent Optimize in the next version:

Gain in the initial state (with cap. C0) Noise: blocking of voltage references Active filter in the feedback of the output stage Resistance of the capacitance switches

  • P. Wieczorek, H. Flemming and H. Deppe

Experiment Electronics

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SLIDE 16

Outline Architecture and Properties Mode of Operation Measured Results Summary and Outlook Summary Outlook Noise Calc. Backup

First customer is beam diagnostics for the readout of the SEM - grids A 4 channel prototyp is submitted in summer 2018

  • P. Wieczorek, H. Flemming and H. Deppe

Experiment Electronics

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SLIDE 17

Outline Architecture and Properties Mode of Operation Measured Results Summary and Outlook Summary Outlook Noise Calc. Backup

Noise calculations for the input transistor as dominant noise source ENC 2

th[e2] = 10 · kB · T

8 · q2 C 2

T

τs ·

  • (kx · W /L · Ids)

(1) ENC 2

1/f [e2] =

4 · Kf C 2

  • x · q2

C 2

T

W · L (2) ENC 2

DET [e2] = 2

q · Idet · τs (3) ENC 2

tot = ENC 2 th + ENC 2 1/f + ENC 2 DET

(4)

  • P. Wieczorek, H. Flemming and H. Deppe

Experiment Electronics

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SLIDE 18

Outline Architecture and Properties Mode of Operation Measured Results Summary and Outlook Summary Outlook Noise Calc. Backup

Optimise transistor parameter W /L and Ids

Input transistor ratio W /L high ⇒ large input capacitance Current through input transistor large ⇒ high power consump.

ENC Calculation f(x,y) 1 10 100 1000 10000 Transistor W [µm] 1e-06 1e-05 0.0001 0.001 0.01 0.1 1 Input Transistor Current [A] 1000 2000 3000 4000 5000 6000 7000 8000 ENC [e-] 1000 2000 3000 4000 5000 6000 7000 8000

  • P. Wieczorek, H. Flemming and H. Deppe

Experiment Electronics

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Outline Architecture and Properties Mode of Operation Measured Results Summary and Outlook Summary Outlook Noise Calc. Backup

1800 2000 2200 2400 2600 2800 3000 3200 3400 10 20 30 40 50 ENCT [e-] Capacitance Cf [pF]

  • Calc. Noise

f(x)=a*x+b

Small capacitance for small signals ⇒ better SNR

  • P. Wieczorek, H. Flemming and H. Deppe

Experiment Electronics

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SLIDE 20

Outline Architecture and Properties Mode of Operation Measured Results Summary and Outlook Summary Outlook Noise Calc. Backup

Layout input transistor with W /L: 35 556 (256 × 25/0.18) Input transistor area on chip: 330 µm × 95 µm

  • P. Wieczorek, H. Flemming and H. Deppe

Experiment Electronics

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SLIDE 21

Outline Architecture and Properties Mode of Operation Measured Results Summary and Outlook Summary Outlook Noise Calc. Backup

CSA based on folded cascode architecture

Vbn Vbp Ig I1 I2 MP1 MN2 Vbc MN4 MP3 Vk Vin Vout

No. Current (TT ; SS ; FF) Unit Ig 3.1 ; 2.6 ; 3.81 mA I1 2.6 ; 2.2 ; 3.25 mA I2 0.5 ; 0.4 ; 0.55 mA MN2 MP1 MP3 MN4 Unit Number 256 20 10 8 1 W 25 15 60 2.5 µm L 0.18 1 0.5 1.5 µm Ids(TT) 2.6 3.1 0.5 0.5 mA

  • P. Wieczorek, H. Flemming and H. Deppe

Experiment Electronics