Optimal Partitioned Fault-Tolerant Bus Layout for Reducing Power in - - PowerPoint PPT Presentation

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Optimal Partitioned Fault-Tolerant Bus Layout for Reducing Power in Nanometer Designs

Shanq-Jang Ruan1, Edwin Naroska2 Chun-Chin Chen1

1National Taiwan University of

Science and Technology Taipei, Taiwan

2Fraunhofer IMS

Duisburg, Germany

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Outline

• Introduction

– Why do we need low power – Source of Power Dissipation – Coupling effect in deep-submicro technology – Motivation and Observation

• Permutation and Spacing for Low Power Bus Design

– Coupling Capacitance Model – Permutation Technique – Spacing Technique

• Bus Partition Flow
• Low Power Fault-Tolerant Bus Architecture
• Graph Theory Algorithm for Fault-Tolerant Bus

Layout Optimization

• Experimental Results
• Conclusion

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Introduction

• Why do we need low power-
• Why we need low power fault-tolerant bus design

in VDSM

– Power has become a critical concern for nowadays design for hand-held and high-performance systems. – In VDSM era, on-chip interconnect contribution about 15% to 30% total power dissipation in modern microprocessors. – For low power and reliability concerns, a fault-tolerant bus could be used to reducing power while increasing reliability.

Battery Life Reliability

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Introduction

• Source of Power Dissipation-

leakage short dynamic avg

P P P P + + = ) ( 2 1

2

sw E V C P

dd L dynamic

× × =

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Introduction

• Coupling Effect in DSM Technology-

This effect also introduce power dissipation

Coupling power becomes significant in deep-submicro. For example, in standard 0.13µm technologies with minimum distance between bus lines, the ratio of coupling and line capacitances is great than eight.

d A C ε =

d A

• Geometry downscaling of digital circuits (deep

submicron) increases coupling capacitance C between adjacent wires

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Introduction

• Motivation and Observation-
• From 12 SPEC2000 benchmark programs, the

number of different transition patterns is far less than theoretical number (232×232).

• Signal statistics can be used to decrease

coupling!

9788 7655 5302 13547 5778 30714 33408 12497 6011 85728 15546 5914 Tran. Types ammp equake art mesa bzip2 vorex perlbmk parser mcf gcc vpr gzip Prog.

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Modeling Coupling Effect for Adjacent Wires

• One wire is static

Dissipated power: λ

• Both wires transition to

same value

Dissipated power: 0

• Wires transition in
• pposite directions

Dissipated power: 4 λ C C C C C C

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Coupling Effect Table

• Normalized coupling effect table

1 1 11 1 4 1 10 1 4 1 01 1 1 00 Old value 11 10 01 00 new value

C

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Problem Formulation

• Based on probabilities

p01,00 (i, j), p10,00 (i, j), p11,00 (i, j), p00,01 (i, j), p10,01 (i, j), …, p01,11(i, j) the crosstalk caused by a wire pair (i, j) can be formulated as:

• Coupling Effect between

wires:

) , ( 4 ) , ( 4 ) , ( ) , ( ) , ( ) , ( ) , ( ) , ( ) , ( ) , ( ) , (

01 , 10 10 , 01 01 , 11 00 , 10 11 , 01 10 , 00 10 , 11 00 , 01 11 , 10 01 , 00

j i p j i p j i p j i p j i p j i p j i p j i p j i p j i p j i xtalk + + + + + + + + + =

) , (

1 min + =

⋅ = = ∑

i i i n i i eff

w w xtalk d A c with c xtalk ε

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Permutation

Coupling effect (power dissipation) is

dependent on signal statistics of neighboring wires

W5 w0 w1 w2 w3 W4

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Spacing approach #1/2

• Spacing approaches

– Equal spacing – Coupling aware spacing

• “Equal” spacing

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Spacing approach #2/2

• Coupling between adjacent wires is typically different

due to traffic

• “Coupling aware” spacing

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Do We Need Extra Area for Enlarging Wire Spacing?

• Example:

– All digital phase locking loop (ADPLL) – Area utilization is set to 82% for routing with Astro (Synopsys) by different width:length ratios.

1 1 1 2 1 9 3 … … …

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Bus Partition Flow

• Bus Partition
• Optimization with Permutation and Spacing

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Partitioned fault-tolerant bus Architecture

Receiver

BUS BUS

Reduced coupling By spacing

Wire Permutation

Perm Encoder Perm Decoder

Parity Encoder Decoder & Correcter

Sender

parity bits data bits Wire Permutation Wire Permutation Wire Permutation

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Graph Theory Algorithm for Fault- tolerant Bus Layout Optimization

• Graph theory for permutation

– This problem is similar to the traveling-salesman problem

• r finding minimum Hamilton path problem .

– To find a optimization solution in a polynomial-time

• Graph theory for spacing

– Depend on the result of permutation – Got more coupling in neighbor wires, got more extra space in neighbor wires of bus.

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Graph theory for permutation

• Using a heuristic algorithm similar to Kruskal’s

minimum spanning tree algorithm.

– the edge with the smallest weight is selected that does not cause a cycle and does not increase the degree of a node to more than two

⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎣ ⎡ = 4 5 4 5 3 4 5 4 5 7 5 5 1 4 2 4 4 1 3 3 5 5 4 3 3 3 7 2 3 3 M

Transfer to graph and find the minimum hamiltonian path

V5 V1 V2 V3 V4 V6 3 3 4 3 3 2 7 5 4 4 4 1 5 5 5

1 2 3 4 3

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Graph theory for spacing

• Using the result of permutation and extra space K to

assign space

V1 V2 V3 V4 V5 V6

V5 V1 V2 V3 V4 V6 3 3 4 2 1 1 2 1 −

+ ⋅ ⋅ ⋅ + + × =

n i i

w w w w K d

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Graph theory for spacing

• Using the result of permutation and extra space K to

assign space

V5 V6 V1 V4 V3 V2

V5 V1 V2 V3 V4 V6 3 3 4 2 1 1 2 1 −

+ ⋅ ⋅ ⋅ + + × =

n i i

w w w w K d

min 1

d d +

min 5

d d +

min 3

d d +

min 2

d d +

min 4

d d +

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Simulation Environment

• Instruction bus of PISA

processor architecture (derived from MIPS-IV ISA)

• 12 SPEC2000 benchmark

programs

• 20% additional space
• The bus is with 1000µm long,

0.14µm width and 0.25µm height based on 90nm technology process

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Power Reduction Compared with the Original bus Architecture

5 10 15 20 25 30 35 40 45 50 gzip vpr mesa art mcf equake ammp parser perlbmk bzip2 vortex gcc perm(no extra space) perm with extra 20*dmin space perm+spacing with extra 20*dmin space

• Fig. 9

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Power Reduction for Different Parity Bit Positions and Spacing Approaches

• 15
• 10
• 5

5 10 15 20 25 30 35 gzip vpr mesa art mcf equake ammp parser perlbmk bzip2 vortex gcc parity bits in last position parity bits average inserted perm perm+spacing

• Fig. 10

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Theoretical Optimization Results vs. Realistic Values

5 10 15 20 25 30 35 40 g z i p v p r m e s a a r t m c f e q u a k e a m m p p a r s e r p e r l b m k b z i p 2 v

• r

t e x g c c perm (H SP ICE ) perm (th eoretical)

• Fig. 11

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Coupling Effect Reduction for Different Partitioned Methods

5 10 15 20 25 30 35 40 g z i p v p r m e s a a r t m c f e q u a k e a m m p p a r s e r p e r l b m k b z i p 2 v

• r

t e x g c c perm(no partition) perm+partition parity perm+partion parity and instru

• Fig. 12

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Power Reduction of Partitioned Fault-tolerant Bus

5 10 15 20 25 30 35 40 g z i p v p r m e s a a r t m c f e q u a k e a m m p p a r s e r p e r l b m k b z i p 2 v

• r

t e x g c c perm+spacing(no partition) perm+spacing+partition parity perm+spacing+partition parity with shield

• Fig. 13

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Conclusion

• Our fault-tolerant bus architecture using

graph theory algorithm can efficient reduce coupling compared to realistic experimental result.

• Nearly no additional area and timing delay
• Finding a optimization solution in a

polynomial-time

• Partition fault-tolerant bus architecture

using graph theory algorithm also can efficient save energy.

• Easy to merge into nowadays’ design flow

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Thanks for Your Attention!