Sequential Circuit Test Generation 1 Introduction Almost all - - PowerPoint PPT Presentation

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Sequential Circuit Test Generation

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Introduction

• Almost all practical digital systems are sequential

circuits.

• Their testing is more complex than that of

combinational circuits, due to two reasons:

1.

Internal memory states

• State not known at the beginning of test.
• The test must initialize the circuit to a known state.

2.

Long test sequences

• <continued on next slide>

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2.

Long test sequences

• A test for a fault in a sequential circuit essentially

consists of three parts:

–

Initialization of the internal memory.

–

Combinational test to activate the fault, and bring its effect to the boundary of the combinational logic.

–

If the fault is in the memory elements, observation of the faulty state in one of the primary outputs.

• Thus the test for a fault may be a sequence of several

vectors that must be applied in the specified order.

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Model of a Synchronous Sequential Circuit

Combinational Logic Flip-flops

PI PO Clock

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Assumptions

We consider synchronous sequential circuits. All memory elements are under the control of a

clock signal.

Vectors at the primary inputs are synchronized

with the clock.

A new vector is applied just after the active edge of the

clock.

To avoid any simultaneous change of the data and clock

signals at a flip-flop (possibly causing a race).

Outputs reach their steady-state values just before the

next active edge of the clock.

Time of signal propagation through the

combinational logic does not exceed the clock period.

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A Simplified Model

The combinational part is modeled at the gate level. All single stuck-at faults are considered in it. Flip-flops are treated as ideal memory elements. Clock signal is not explicitly represented, and no

faults in the clock signals are modeled.

Internal faults in flip-flops are not modeled. Input/output faults on flip-flops are modeled as

faults on output and input signals of the combinational logic.

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Test Generation Methods

• Can be classified into two categories:

1.

Time frame expansion

• A model of the circuit is created such that tests can be

generated by a combinational ATPG tool.

• Very efficient for circuits described at the gate level.
• Efficiency degrades significantly with cyclic structure,

multiple-clocks, or asynchronous logic.

2.

Simulation-based methods

• A fault simulator and a test vector generator are used to

derive tests.

• Circuits modeled at other levels (RTL, transistor, etc.)

can be treated.

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Time Frame Expansion Method

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Point to Note

• Two basic differences between combinational and

sequential circuits.

1.

A test for a fault in a sequential circuit may consist of several vectors.

• A combinational ATPG is capable of generating only a

single vector for a target fault.

2.

Presence of uninitialized states of the sequential circuit.

• A combinational ATPG can deal with unknown (X)

signal states.

• 5-valued logic, usually effective for combinational

circuits, is insufficient for sequential circuits.

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Example: A Serial Adder

FF An Bn Cn Cn+1 Sn s-a-0 1 1 1 1 1 X X X D D Combinational logic

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How the adder works? Initialization: say, by applying 00 input. Serial addition: applied bit by bit. To apply combinational ATPG procedures: We can “unroll” the sequential circuit into a larger

combinational circuit.

Called time frame expansion. For the adder example: The fault cannot be propagated to Sn. We repeat the combinational logic twice to

generate a 2-vector test.

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Time-Frame Expansion

An Bn FF Cn Cn+1

1 X X

Sn

s-a-0 1 1 1 1 D D Combinational logic

Sn-1

s-a-0 1 1 1 1 X D D Combinational logic

Cn-1

1 1 D D X

An-1 Bn-1

Time-frame -1 Time-frame 0

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The leftmost block has its state input in the X state. Since the fault is present in all frames, it is modeled

as a multiple fault.

It is possible to propagate a D to the output. All four input bits justified to be 1’s. Thus the test is an initialization vector 11 followed

by another 11 vector that produces a D at the

• utput.

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Concept of Time-Frames

If the test sequence for a single stuck-at fault contains

n vectors,

Replicate combinational logic block n times Place fault in each block Generate a test for the multiple stuck-at fault using

combinational ATPG with 9-valued logic Comb. block Fault

Time- frame Time- frame

• 1

Time- frame

• n+1

Unknown

• r given
• Init. state

Vector 0 Vector -1 Vector -n+1 PO 0 PO -1 PO -n+1 State variables Next state

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Necessity of Nine-Valued Logic

Five valued system 0, 1, D, D’, X Nine valued system 0, 1, 1/0, 0/1, 1/X, 0/X, X/0, X/1, X We show an example to illustrate the advantage of

the nine-valued system.

A s-a-1 fault cannot be propagated using 5-valued

logic.

Can be propagated using 9-valued logic.

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Example for Logic Systems

FF2 FF1 A B s-a-1

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Five-Valued Logic (Roth) 0,1, D, D, X

A B X X X s-a-1 D A B X X X s-a-1 D FF1 FF1 FF2 FF2 D D Time-frame -1 Time-frame 0

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Nine-Valued Logic (Muth)

0,1, 1/0, 0/1, 1/X, 0/X, X/0, X/1, X

A B X X X s-a-1 0/1 A B 0/X 0/X 0/1 X s-a-1 X/1 FF1 FF1 FF2 FF2 0/1 X/1 Time-frame -1 Time-frame 0

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Implementation of ATPG

Select a PO for fault detection based on drivability

analysis.

Place a logic value, 1/0 or 0/1, depending on fault

type and number of inversions.

Justify the output value from PIs, considering all

necessary paths and adding backward time-frames.

If justification is impossible, then use drivability to

select another PO and repeat justification.

If the procedure fails for all reachable POs, then the

fault is untestable.

If 1/0 or 0/1 cannot be justified at any PO, but 1/X or

0/X can be justified, the the fault is potentially detectable.

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Drivability Example

d(0/1) = 4 d(1/0) = (CC0, CC1) = (6, 4) s-a-1 (4, 4) (10, 15) (11, 16) (10, 16) (22, 17) (17, 11) (5, 9) d(0/1) = 9 d(1/0) = d(0/1) = 109 d(1/0) = d(0/1) = 120 d(1/0) = 27 d(0/1) = d(1/0) = 32 (6, 10) 8 8 8 8 FF d(0/1) = d(1/0) = 20 8 CC0 and CC1 are SCOAP combinational controllabilities d(0/1) and d(1/0) of a line are effort measures for driving a specific fault effect to that line

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Complexity of ATPG

Synchronous circuit -- All flip-flops controlled by clocks; PI and

PO synchronized with clock: Cycle-free circuit – No feedback among flip-flops: Test generation for a fault needs no more than dseq + 1 time- frames, where dseq is the sequential depth. Cyclic circuit – Contains feedback among flip-flops: May need 9Nff time-frames, where Nff is the number of flip-flops.

Asynchronous circuit – Higher complexity!

Time- Frame Time- Frame max-1 Time- Frame max-2 Time- Frame

• 2

Time- Frame

• 1

S0 S1 S2 S3 Smax max = Number of distinct vectors with 9-valued elements = 9Nff

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Cycle-Free Circuits

Characterized by absence of cycles among flip-flops and

a sequential depth, dseq.

dseq is the maximum number of flip-flops on any path

between PI and PO.

Both good and faulty circuits are initializable. Test sequence length for a fault is bounded by dseq + 1.

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Cycle-Free Example

F1 F2 F3 Level = 1 2 F1 F2 F3 Level = 1 2 3 3

dseq = 3

s - graph Circuit All faults are testable.

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Cyclic Circuit Example

F1 F2 CNT Z Modulo-3 counter s - graph F1 F2

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Modulo-3 Counter

Cyclic structure Sequential depth is undefined. Circuit is not initializable. No tests can be generated for any stuck-at fault. After expanding the circuit to 9Nff = 81, or fewer, time-

frames ATPG program calls any given target fault untestable.

Circuit can only be functionally tested by multiple

• bservations.

Functional tests, when simulated, give no fault

coverage.

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Adding Initializing Hardware

F1 F2 CNT Z Initializable modulo-3 counter s - graph F1 F2 CLR s-a-0 s-a-1 s-a-1 s-a-1

Untestable fault Potentially detectable fault

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Benchmark Circuits

Circuit PI PO FF Gates Structure

• Seq. depth

Total faults Detected faults Potentially detected faults Untestable faults Abandoned faults Fault coverage (%)

• Max. sequence length

Total test vectors Gentest CPU s (Sparc 2) s1196 14 14 18 529 Cycle-free 4 1242 1239 3 99.8 3 313 10 s1238 14 14 18 508 Cycle-free 4 1355 1283 72 94.7 3 308 15 s1488 8 19 6 653 Cyclic

• 1486

1384 2 26 76 93.1 24 525 19941 s1494 8 19 6 647 Cyclic

• 1506

1379 2 30 97 91.6 28 559 19183

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Asynchronous Circuit

An asynchronous circuit contains unclocked memory. Often realized by combinational feedback. Almost impossible to build, let alone test, a large

asynchronous circuit.

Typical examples of asynchronous circuits: Clock generators Signal synchronizers Flip-flops Many large synchronous systems contain small portions of

localized asynchronous circuitry.

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Asynchronous Model

Clocked Flip-flops Feedback delays Synchronous PIs Synchronous POs System Clock, CK Fast model Clock, FMCK CK CK Feedback-free Combinational Logic

C

Combinational Feedback Paths PPO PPI

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• To isolate the combinational logic, we split the

asynchronous logic into two parts:

1.

Feedback-free combinational logic.

2.

A set of delay elements synchronized with a fast clock FMCK.

• FMCK runs much faster than the system clock.
• Its purpose is to repeatedly evaluate the combinational

logic and stabilize asynchronous signals before CK clocks the flip-flops.

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• A time-frame expansion type of test generator deals

with the circuit in two phases:

1.

System clock (CK) phase.

• The operation of the circuit is synchronous with respect

to CK.

2.

Fast modeling clock (FMCK) phase.

• Following the system clock phase, which provides new

inputs to the combinational logic, a series of fast time- frames exercise the logic until signals become stable.

• For practical reasons, a small fixed number of time-

frames is used.

• If it does not become stable, assume oscillation.

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Time-Frame Expansion

Time-frame k Time-frame

• k+1

Time-frame

• k-1

C FMCK C FMCK C FMCK C CK Asynchronous feedback stabilization PI PO Feedback set PPI PPO Feedback set Vector k

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Asynchronous Example

A

s-a-0 s-a-0 s-a-0 s-a-0 s-a-0 s-a-0 s-a-0 s-a-1 1 1 1 1 Vectors 1 2 3 4 1 1 X X 1 1 1 1 Outputs 1 2 3 4

Gentest results:

Faults: total 23, detected 15, untestable 8 (shown in red), potentially detectable none Vectors: 4 Sparc 2 CPU time: test generation 33ms, fault simulation 16ms R S Q Q’

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Observations

Not all faults identified as untestable are really

untestable.

They are actually untestable by a single-vector

test.

The s-a-0 fault on the Q input of the OR gate A is

testable by two vectors, (S,R) = (1,0), (0,0).

Fortunately, the generated test sequence does not

cause a race condition in the fault-free circuit.

Such race conditions should be found by a

simulator, and the vectors causing them should be discarded or modified.

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Summary

Combinational ATPG algorithms are extended:

Time-frame expansion unrolls time as combinational array Nine-valued logic system Justification via backward time

Cycle-free circuits:

Require at most dseq time-frames Always initializable

Cyclic circuits:

May need 9Nff time-frames Circuit must be initializable Partial scan can make circuit cycle-free

Asynchronous circuits:

High complexity Low coverage and unreliable tests Simulation-based methods are more useful