Terminal and Order Reduction of Multi-Input/Output LTI Systems Andr - - PowerPoint PPT Presentation

Summer School on Numerical Linear Algebra for Dynamical and High-Dimensional Problems, Trogir, Croatia, October 12, 2011

Terminal and Order Reduction of Multi-Input/Output LTI Systems

Andr´ e Schneider

Computational Methods in Systems and Control Theory Max Planck Institute for Dynamics of Complex Technical Systems Magdeburg, Germany

Max Planck Institute Magdeburg

• A. Schneider, Terminal and Order Reduction of MIMO LTI Systems

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Overview

The Setting

Linear Time Invariant Descriptor System

E ˙ x(t) = Ax(t) + Bu(t), x(0) = x0, y(t) = Cx(t) + Du(t), with A, E ∈ Rn×n, B ∈ Rn×m, C T ∈ Rn×p, D ∈ Rp×m (mostly in application D ≡ 0), x ∈ Rn containing the generalized state space variables, u ∈ Rm the vector of input variables, y ∈ Rp the output vector, and x0 ∈ Rn the initial value.

Max Planck Institute Magdeburg

• A. Schneider, Terminal and Order Reduction of MIMO LTI Systems

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Overview

The Setting

Linear Time Invariant Descriptor System

E ˙ x(t) = Ax(t) + Bu(t), x(0) = x0, y(t) = Cx(t) + Du(t), with A, E ∈ Rn×n, B ∈ Rn×m, C T ∈ Rn×p, D ∈ Rp×m (mostly in application D ≡ 0), x ∈ Rn containing the generalized state space variables, u ∈ Rm the vector of input variables, y ∈ Rp the output vector, and x0 ∈ Rn the initial value. Either m, p ∈ O(n),

Max Planck Institute Magdeburg

• A. Schneider, Terminal and Order Reduction of MIMO LTI Systems

2/9

Overview

The Setting

Linear Time Invariant Descriptor System

E ˙ x(t) = Ax(t) + Bu(t), x(0) = x0, y(t) = Cx(t) + Du(t), with A, E ∈ Rn×n, B ∈ Rn×m, C T ∈ Rn×p, D ∈ Rp×m (mostly in application D ≡ 0), x ∈ Rn containing the generalized state space variables, u ∈ Rm the vector of input variables, y ∈ Rp the output vector, and x0 ∈ Rn the initial value. Either m, p ∈ O(n), or m ∈ O(n) and p ≪ n,

Max Planck Institute Magdeburg

• A. Schneider, Terminal and Order Reduction of MIMO LTI Systems

2/9

Overview

The Setting

Linear Time Invariant Descriptor System

E ˙ x(t) = Ax(t) + Bu(t), x(0) = x0, y(t) = Cx(t) + Du(t), with A, E ∈ Rn×n, B ∈ Rn×m, C T ∈ Rn×p, D ∈ Rp×m (mostly in application D ≡ 0), x ∈ Rn containing the generalized state space variables, u ∈ Rm the vector of input variables, y ∈ Rp the output vector, and x0 ∈ Rn the initial value. Either m, p ∈ O(n), or m ∈ O(n) and p ≪ n, or vise versa.

Max Planck Institute Magdeburg

• A. Schneider, Terminal and Order Reduction of MIMO LTI Systems

2/9

Overview

The Setting

Linear Time Invariant Descriptor System

E ˙ x(t) = Ax(t) + Bu(t), x(0) = x0, y(t) = Cx(t) + Du(t), with A, E ∈ Rn×n, B ∈ Rn×m, C T ∈ Rn×p, D ∈ Rp×m (mostly in application D ≡ 0), x ∈ Rn containing the generalized state space variables, u ∈ Rm the vector of input variables, y ∈ Rp the output vector, and x0 ∈ Rn the initial value. Either m, p ∈ O(n), or m ∈ O(n) and p ≪ n, or vise versa. Applying the Laplace transform leads to

Transfer Function

H(s) = C(sE − A)−1B, s ∈ C.

Max Planck Institute Magdeburg

• A. Schneider, Terminal and Order Reduction of MIMO LTI Systems

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Overview

Moore’s Law

Transistor counts for integrated circuits plotted against their dates of introduction. The curve shows Moore’s law - the doubling of transistor counts every two years. Source: Wikipedia Max Planck Institute Magdeburg

• A. Schneider, Terminal and Order Reduction of MIMO LTI Systems

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Overview

An Old Slide of 2008

Wafer Development

Integrated circuits (ICs) are miniaturized electronic devices. Recently, use of nanometer-scale chip manufacturing process, increasing number of (parasitic) elements, and production of multi-layered ICs.

source: Qimonda AG

Today, the Intel Core 2 Extreme (Conroe XE) CPU has about 291 million transistors, produced with a 65 nanometer chip manufacturing process.

Max Planck Institute Magdeburg

• A. Schneider, Terminal and Order Reduction of MIMO LTI Systems

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Overview

Version 10/2011

Wafer Development

Integrated circuits (ICs) are miniaturized electronic devices. Recently, use of nanometer-scale chip manufacturing process, increasing number of (parasitic) elements, and production of multi-layered ICs.

Altera Stratix IV EP4SGX230 FPGA on a PCB, source: Altera Corporation

Today: 2011 CPU - Intel Xeon Westmere-EX - 2.6 billion transistors (32nm), 2010 GPU - Nvidia GF100 - 3.0 bn (40nm), 2011 FPGA - Altera Stratix V - 3.8 bn (28nm).

Max Planck Institute Magdeburg

• A. Schneider, Terminal and Order Reduction of MIMO LTI Systems

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Overview

Animation of a multi-layered IC wiring

Multi-layered IC wiring leads to: very complex structure, a lot of interactions within the IC, large parasitic subcircuits with a large number of terminals, a system described at the beginning of the talk.

Wikipedia image: Silicon chip 3d.png

Examples are power grids and clock distribution networks.

Max Planck Institute Magdeburg

• A. Schneider, Terminal and Order Reduction of MIMO LTI Systems

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Overview

Schematic Representation

inputs u(t)

H(s)

• utputs y(t)

Max Planck Institute Magdeburg

• A. Schneider, Terminal and Order Reduction of MIMO LTI Systems

7/9

Overview

Schematic Representation

u(t)

Hr(s)

y(t)

Max Planck Institute Magdeburg

• A. Schneider, Terminal and Order Reduction of MIMO LTI Systems

7/9

Overview

Schematic Representation

u(t)

˜ Hr(s)

y(t)

Max Planck Institute Magdeburg

• A. Schneider, Terminal and Order Reduction of MIMO LTI Systems

7/9

Overview

Schematic Representation

u(t) ?

˜ Hr(s)

y(t)

?

Max Planck Institute Magdeburg

• A. Schneider, Terminal and Order Reduction of MIMO LTI Systems

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Overview

Existing Methods

Methods which try to get a hand on the problem of many terminals: First ideas: RLP-Algorithm [Jain et al. 2004], RecMOR, SVDMOR [Feldmann, Liu 2004],

Max Planck Institute Magdeburg

• A. Schneider, Terminal and Order Reduction of MIMO LTI Systems

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Overview

Existing Methods

Methods which try to get a hand on the problem of many terminals: First ideas: RLP-Algorithm [Jain et al. 2004], RecMOR, SVDMOR [Feldmann, Liu 2004], ESVDMOR [Liu, Tan et al. 2007] = ⇒ SyreNe,

Max Planck Institute Magdeburg

• A. Schneider, Terminal and Order Reduction of MIMO LTI Systems

8/9

Overview

Existing Methods

Methods which try to get a hand on the problem of many terminals: First ideas: RLP-Algorithm [Jain et al. 2004], RecMOR, SVDMOR [Feldmann, Liu 2004], ESVDMOR [Liu, Tan et al. 2007] = ⇒ SyreNe, TermMerg approach [Liu, Tan et al. 2007],

Max Planck Institute Magdeburg

• A. Schneider, Terminal and Order Reduction of MIMO LTI Systems

8/9

Overview

Existing Methods

Methods which try to get a hand on the problem of many terminals: First ideas: RLP-Algorithm [Jain et al. 2004], RecMOR, SVDMOR [Feldmann, Liu 2004], ESVDMOR [Liu, Tan et al. 2007] = ⇒ SyreNe, TermMerg approach [Liu, Tan et al. 2007], Interpolation based methods [Antoulas, Lefteriu 2009],

Max Planck Institute Magdeburg

• A. Schneider, Terminal and Order Reduction of MIMO LTI Systems

8/9

Overview

Existing Methods

Methods which try to get a hand on the problem of many terminals: First ideas: RLP-Algorithm [Jain et al. 2004], RecMOR, SVDMOR [Feldmann, Liu 2004], ESVDMOR [Liu, Tan et al. 2007] = ⇒ SyreNe, TermMerg approach [Liu, Tan et al. 2007], Interpolation based methods [Antoulas, Lefteriu 2009], Approaches based on graph theory [Rommes, Schilders, Ionutiu 2010],

Max Planck Institute Magdeburg

• A. Schneider, Terminal and Order Reduction of MIMO LTI Systems

8/9

Overview

Existing Methods

Methods which try to get a hand on the problem of many terminals: First ideas: RLP-Algorithm [Jain et al. 2004], RecMOR, SVDMOR [Feldmann, Liu 2004], ESVDMOR [Liu, Tan et al. 2007] = ⇒ SyreNe, TermMerg approach [Liu, Tan et al. 2007], Interpolation based methods [Antoulas, Lefteriu 2009], Approaches based on graph theory [Rommes, Schilders, Ionutiu 2010], Balanced truncation for many terminals (BTMT) [Benner, S. 2011].

Max Planck Institute Magdeburg

• A. Schneider, Terminal and Order Reduction of MIMO LTI Systems

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Overview

Schematic Representation of TermMerg

inputs u(t)

H(s)

• utputs y(t)

Max Planck Institute Magdeburg

• A. Schneider, Terminal and Order Reduction of MIMO LTI Systems

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Overview

Schematic Representation of TermMerg

H(s)

Max Planck Institute Magdeburg

• A. Schneider, Terminal and Order Reduction of MIMO LTI Systems

9/9

Overview

Schematic Representation of TermMerg

Hr(s)

Max Planck Institute Magdeburg

• A. Schneider, Terminal and Order Reduction of MIMO LTI Systems

9/9