Tutorial on Design For Manufacturability for Physical Design - - PowerPoint PPT Presentation

Tutorial on Design For Manufacturability for Physical Design

Andrzej J. Strojwas

PDF Solutions Inc., San Jose, CA & Carnegie Mellon University, Pittsburgh, PA

2005 ISPD, San Francisco, CA April 5, 2005

Overview of Presentation

Yield Loss Mechanism Evolution Classification of DFM Approaches True DFM: Defining Proactive DFM Necessary Conditions for Proactive DFM Process Characterization Design Flows that Provide Proactive DFM DFM Results Looking into the Future: Extreme Layout Regularity

Yield, Performance, Profitability

The Evolution of Product Yields

Random defects are no longer the dominant yield loss mechanism

• Yields are limited by design features, systematic and parametric effects

Yield Limiters by Technology Node

40% 50% 60% 70% 80% 90% 100% . 8 u m . 5 u m . 3 5 u m . 2 5 u m . 1 8 u m . 1 3 u m 9 n m

Technology Yield

Random Defect Limited Yield Design Feature Limited Yield Total Yield

Yield, Performance, Profitability

Random Yield Loss Mechanisms – Al Interconnect Contact and via opens due to formation defectivity Active, poly and metal shorts and opens due to particle defects Random Yield Loss Mechanisms Type Material

• pens

Material shorts

Yield, Performance, Profitability

Systematic Yield Loss Mechanisms - Cu Interconnect

Misalignment, line-ends/borders Contact/via opens due to local neighborhood effects (e.g. pitch/hole size) Leakage from STI related stress Impact of micro/macro loading design rule marginalities Systematic

Yield Loss Mechanisms Type

Failure Rate 20 40 60 80 100 120 140 160 0.4 1.8 4.2 9 Pitch (um) Via Failure Rate (fpb)

Sparse neighborhood

Yield, Performance, Profitability

Systematic Yield Loss: Printability – Nanometer Era

Material opens Poor contact coverage due to misalignment and defocus/pull back Systematic

Yield Loss Mechanisms Type

Poly/Metal shorts

Yield, Performance, Profitability

Parametric Yield Loss Mechanisms – Nanometer Era

Non-physical corner modeling Device mismatch Dummy fill parasitic effects Performance variation from lithography effects e.g., contact/via coverage, active/poly flaring, CD variation Parametric

Yield Loss Mechanisms Type

ACLV / CD Variation Environment dependent poly CD variation

• 10.50
• 10.00
• 9.50
• 9.00
• 8.50
• 8.00
• 7.50
• 7.00
• 6.50
• 6.00

300.00 400.00 500.00 600.00 700.00 800.00 Idrive Ioff Env I Env II Env III

Yield, Performance, Profitability

Technology Challenges: Implications for Manufacturability 65nm

Litho: OPC/PSM integration issues w/photo window (DOF) Front-end/Transistor Layout dependent performance Product ramp issues Parametric variations - > yield loss

65nm

Litho: OPC/PSM integration issues w/photo window (DOF) Front-end/Transistor Layout dependent performance Product ramp issues Parametric variations - > yield loss

45nm

Litho: Layout pattern dependence, Scanner NA, Immersion litho, OPC/PSM integration, issues w/photo window (DOF) Front end/Transistor New transistor architectures (UTB, DG SOI) Product ramp issues Reliability assurance

45nm

Litho: Layout pattern dependence, Scanner NA, Immersion litho, OPC/PSM integration, issues w/photo window (DOF) Front end/Transistor New transistor architectures (UTB, DG SOI) Product ramp issues Reliability assurance

90nm

Back-end integration issues Low k: stress and reliability CMP - multi-layer topography issues Product ramp issues Variability Yield-performance tradeoffs

90nm

Back-end integration issues Low k: stress and reliability CMP - multi-layer topography issues Product ramp issues Variability Yield-performance tradeoffs

Yield, Performance, Profitability

DFM is a Business Opportunity "Seamless" DFM Can Contribute 5% More Good Die

What's 5% more good die worth? $50M over the life of a cell phone

$80M over the life of a game chip

$100M per year per fab at 90nm

Yield, Performance, Profitability

A Brief History of DFM

Design rules guarantee yield!…well, not really… …then recommended rules …and opportunistic design data base post-processing to enforce them Functional Yield means Rules The corners represent the process …The corners don’t represent the process but they are conservative …Within chip variations are important so..

• Restrict transistor layouts?
• Statistical timing simulation?

Performance Yield is Covered by Corners

Idsat Distribution

• 500
• 450
• 400
• 350
• 300
• 250
• 200

600 650 700 750 800 850 900 950 1000 1050

NIdsat PIdsat

ASIC Corners Realistic Corners

Yield, Performance, Profitability

Post-GDS Yield Opt. OPC/ RET

Design Design Manufacturing Manufacturing

MDP and Mask Making Yield Ramp IP lib. Design pre-MDP Timing and SI Analyses Physical Verification Physical SP&R

Verification and Yield Opt. Verification and Yield Opt.

Dummy Fill and Cheesing Volume Production Post-GDS Yield Opt. OPC/ RET

Design Design Manufacturing Manufacturing

MDP and Mask Making Yield Ramp IP lib. Design pre-MDP Timing and SI Analyses Physical Verification Physical SP&R

Verification and Yield Opt. Verification and Yield Opt.

Dummy Fill and Cheesing Volume Production

Process Characterization + Yield Modeling

DFM needs to be Proactive Occurring early in the design flow Up-front accurate process characterization Yield modeling to characterize IP and drive EDA tools

Proactive DFM

Designer access to the process is limited Most DFM today is Reactive

• Increase in design cycle time
• Misaligned mask GDSII and

design database

• Risky design feature changes

Yield, Performance, Profitability

Necessary Conditions for Pro-Active DFM

Accurate characterization of design-interactions at target fab(s) Effects modeled across the whole process window Quantification of alternatives that allow EDA tools to make millions of DFM trade-offs Integration early in the design flow where there are more degrees of freedom

• Floor planning
• SP&R

Modifications made prior to verification

Yield, Performance, Profitability

Yield Simulation is Core to Proactive DFM

A yield model for DFM:

• Model of failure rate of a design element (e.g., transistor, contact, via)

as a function of the layout design

• Example:
• What is the failure rate of a single via vs. double?
• What is the probability of a short in two metal lines if there are lots of vias

underneath them

To do this, we need process characterization Yield Simulation allows for better understanding of the DFM universe

Yield, Performance, Profitability

Process Yield Loss Mechanisms

Active Poly Poly C C M1 V1 M1 V1 M2 M2 V2 V2 Mx

Yield Loss Mechanisms Yield Loss Mechanisms

• Layer defect densities
• Attribute dependent failure rates
• Lithography / CMP driven interactions
• …
• Yield Loss Mechanisms (

Yield Loss Mechanisms (YLM’s YLM’s) )

• Root causes of process related yield loss
• Each YLM must be characterized in the process with a specific test

structure – Characterization Vehicle (CV)

Yield, Performance, Profitability

Typical Die Yield Estimation

Model implies that for a given die size, yield is based only upon process maturity – this is not correct

• Yield is different for different IP content
• Process defectivity is different for each module

) (cm area die A ) (1/cm defects mean D yield die Y where e Y

2 2 A D

= = = =

−

,

Die Yield Model

0% 20% 40% 60% 80% 100% 0.5 1 1.5 2

Mean Defectivity (1/cm^2) Die Yield

Area = 2 cm^2 Area = 1.5 cm^2 Area = 1 cm^2 Area = 0.5 cm^2

Yield, Performance, Profitability

Process-Design Interaction

Chip Yield is a strong function of design content

• Physical design features interact with specific module weakness

Memory Logic Memory Logic

Ratio << 1.0 Ratio << 1.0 Ratio >> 1.0 Ratio >> 1.0

LOGIC MEMORYY

Y Y =

Die Content Impact on Yield (~40mm^2 Die Size) 5% 15% 25% 35% 45% 55%

0.0 1.0 2.0 3.0 4.0

Memory/Logic Ratio Yield

Total Yield (130nm) Total Yield (90nm)

Yield, Performance, Profitability

Accurate Process Characterization

Defect Size Distribution by Process Module

Defect Size [um] Defect Density [Defects/cm^2]

• n

distributi t size/coun defect DSD(x) =

Metal Opens/Shorts Metal Opens/Shorts Characterization Vehicle Characterization Vehicle Poly and Active Opens/Shorts Poly and Active Opens/Shorts Characterization Vehicle Characterization Vehicle

Yield, Performance, Profitability

Product Design Attributes SRAM ASIC Logic ROM Analog I/O Custom Logic

• Design Attributes:

Design Attributes:

• Physical design properties that interact with specific module marginalities
• Each attribute can be extracted from physical layout
• Design attribute extraction (DAE) enables quantification of design content specific

YLM models

Design Attributes Design Attributes

• Widths, lengths and spacing
• Counts
• Densities
• Overlaps/enclosures
• …

Yield, Performance, Profitability

Design Attribute Extraction

Contact/Via Count Design Attribute Extraction

Contacts and Vias Count Critical Area Shorts Design Attribute Extraction Defect Diameter [um]

Critical Area [um^2]

Contacts/Via Counts

• N/P Active
• Poly
• V1-Vx

Critical Area Shorts Sensitivities

• AA
• Poly
• M1-Mx

x to ty sensitivi attribute design (x) A

C

=

Yield, Performance, Profitability

Accurate Process Characterization

Process Margin

0.2 0.4 0.6 0.8 1 1.2 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 Spacing Yield 0.05 0.1 0.15 0.2 0.25 0.3 p(spacing)

Layout Metric Misalignment M a s k E r r

• r

DOE on litho parameters RSM of layout metric INPUT: Characterization of litho process statistics

Defocus Exposure

Yield Loss

Defocus 0.1 0.2 0.3 0.4 0.5 0.6 0.7

Exposure 0.1 0.2 0.3 0.4 0.5 0.6 0.7

Yield, Performance, Profitability

PSD: condition 1 PSD: condition2 PSD Analysis Process Margin data from CV

Implicit YLM model: process window effects

Yield, Performance, Profitability

Yield Simulation Results: Yield Impact Matrix

SRAM ASIC Logic ROM Analog I/O Custom Logic

Physical design properties that interact with specific module defectivities Each attribute can be extracted from GDSII Design attribute extraction (DAE) enables quantification of die content specific yield models

Design Attributes Design Attributes

• Widths, lengths and spacing
• Counts
• Densities
• Overlaps/enclosures
• …

YIMP Matrix

Active Random 98% 99% 99% Pattern Dependent 99% 99% 100% Total 97% 98% 99% Poly Random 97% 98% 99% Pattern dependent 94% 95% 99% Total 91% 95% 96% Metal Random 97% 98% 99% Pattern dependent 97% 98% 99% Total 94% 95% 99% Holes 97% 98% 99% Total 81% 82% 99% Metal Islands 87% 89% 90% Pattern Density 91% 93% 94% Narrow Space Wide Neighbor 97% 99% 100% Via induced Metal Shorts 77% 78% 79% Total 62% 64% 64%

Random Defects Systematic

LOGIC

Limited Yield Failure Mode

Full Chip

SRAM

Yield, Performance, Profitability

Yield Simulation Accuracy Yield modeling accuracy is excellent when you characterize right

• Error represents unidentified yield loss mechanisms
• r lack of yield model

Accuracy of Yield Prediction

0% 20% 40% 60% 80% 100% A B C D E F

Product Yield

• 10%
• 8%
• 6%
• 4%
• 2%

0% 2% 4%

Absolute Error

Predicted Actual

• Abs. Error

Yield, Performance, Profitability

Overview of Layout Design for Manufacturability

Critical Area Based Wire Spreading

• Most useful in Al interconnect era (random metal shorts – dominant

yield loss mechanism)

Contact/via Doubling

• Effective in reduction yield losses due to random hole opens (Al & Cu)

Systematic Yield Model Based Local and Global P&R Layout Modifications

• Essential for 3-D topography effects due to Cu CMP and low-k

interconnect

Printability and Performance Variability Driven Layout Generation

• Absolute must in the Nanometer Era
• Pro-active (not afterthought in RET)

Yield, Performance, Profitability

Limited Yield Optimization

Product yields must be optimized by improving LY’s

• LYGAIN ratio of improvement for any specific optimization

Prioritizing which LY’s to improve requires an understanding of the specific Design Manufacturability Objectives Design Manufacturability Objectives

LY(SRAM) LY(ASIC)

LY(ROM)

LY(Analog)

LY(I/O)

LY(Custom)

( ) ( )

variant

• riginal

v variant

• ptimized

v Parametric c, Systemati Random j where Y Y LY

2 1 j v j v j GAIN

= = = =∏ , ,

2 1 Yield, Performance, Profitability

10 20 30 40 50 60

40% 60% 80% 100%

Yield # of lots

Design Manufacturability Objectives

Best Yield Variability Best Average Yield Tailored specifically for a process and product Custom Microprocessors Performance Variability Networking, Graphics, DSP Yield Variability DVD, STB, Cell Phone, Digital Cameras Average Yield

Products Objectives

Customization of DFM objectives

• High volume parts in mature process
• Lower volume parts during ramp

Yield, Performance, Profitability

Enabling Proactive DFM For Designers

Design Flow

RTL Design Hierarchical Floorplan Physical Synthesis Chip Assembly Sign-off

VERIFICATION

Yield Models

Yield View (.pdfm)

DFM Optimized Library Module

Standard IP Platform

DFM Software

Yield Simulation and

• ptimization

Three components to enable Proactive DFM

• DFM library module
• Layout attribute dependent yield models (DFM library view)
• Yield simulation and optimization software

Yield, Performance, Profitability

DFM Variant Generation Flow

Cell Layouts Cell Layouts

Manufacturability Hot Spot Localization Manufacturability Hot Spot Localization Constraint generation Constraint generation Layout Design

DFM Library DFM Library

Hot Spots Minimized? Hot Spots Minimized? No Yes MFG Characterization MFG Characterization Pruning Pruning

DFM Architecture Specifications DFM Architecture Specifications

Average Yield Average Yield Yield Variability Yield Variability Performance Variability Performance Variability Netlist Netlist

Yield, Performance, Profitability

Yield Variants Example

High Density

Random/Systematic Yield Variant Litho hot spots M1 shorts M1 opens Yield/Speed Consistency Variant

+20% area

• 50% FR (ppb)

+40% area

• 50% FR (ppb)
• 85% YV (std.dev)

Yield, Performance, Profitability

Standard Cell Optimization Flow

Litho Environment Hot Spot Analysis Litho Simulated Layout 0.14u Optimized Layout

0.18u

Synthesized Layout

0.16u

Optimized Layout

0.2u

MOS1 d g s b nmos L=0.13u W=1u MOS2 d g s b pmos L=0.13u W=0.8u MOS3 d g s b nmos L=0.13u W=0.7u MOS4 d g s b pmos L=0.13u W=1.2u MOS5 d g s b nmos L=0.13u W=1.3u MOS6 d g s b pmos L=0.13u W=1u

Original Netlist

Contact redundancy definition Spacing rules definition Transitions rules definition Metal islands definition Taps …

Cell Architecture

DFM Library View for EDA

• .pdfm view

.pdfm view includes relevant data to enable EDA tools to make yield tradeoffs

• Process Defectivities
• Design Attributes
• Yield and Manufacturability

Models

• .pdfm data also enables BEOL

routing optimzation

Characteristic Library View Layout GDSII Schematic SPICE Netlist Logic Function Verilog Manufacturability .pdfm Performance .lib P&R Footprint LEF

DFM Library Module Core Libraries Process Characterization Design Attribute Extractions Defectivities

Compiler DFM Library View

“pDfx enabled” P&R

Include yield in the cost function Take advantage of design slacks Timing convergence properties unchanged Global/ Detailed Routing Logic/Physical Synthesis Clock routing Timing Sign-off Post-Routing Optimization

.PDFM

STD.CELL YLM models STD.CELL YLM models BEOL YLM models BEOL YLM models

• Stat. Gate Models

CMP/Litho Models

And the Silicon Says…

• Silicon shows up to 12% GDPW improvement by applying our

Silicon shows up to 12% GDPW improvement by applying our Proactive DFM methodology Proactive DFM methodology

0% 2% 4% 6% 8% 10% 12%

GDPW Improvement (%)

A (0.15um) B (0.13um) C (0.13um) D (0.13um) E (0.13um)

Chip / Technology Percentage GDPW Improvement

• Fabless
• Graphics chip
• Early process

lifecycle

• IDM
• Controller chip
• Mid-process lifecycle
• IDM
• Cell phone chip
• Mid process lifecycle
• IDM
• Set top box
• Mid-process lifecycle
• IDM
• Graphics
• Mature process

Yield, Performance, Profitability

Looking Into the Future: Extreme Layout Regularity

RETs are time-consuming and difficult to optimize for large process windows

• Defocus, Illumination conditions, Pattern neighborhood

Conventional design rules are becoming insufficient to guarantee design’s adherence to RETs

• Increasing need for more geometry regularity by design

Sensitive to grow due to defocus Sensitive to shrink due to defocus Sensitive to exposure variation Sensitive to resist effects

Regular Logic Bricks

Arrays offer advantages for silicon characterization and even inventory, but at a high area penalty Regular Logic Bricks can offer more efficient use of area, and still provide the required regularity

Map a simple set of logic primitives onto regular fabric patterns to form logic bricks

Macro Regularity

Optical proximity: r ≈ 1um 2-3 INVs on boundaries of logic bricks Regular fabric ensures that logic bricks share geometry regularity with all other bricks and registers Fabric “rules” co-optimized for memories, IPs, and bricks Compatible RETs and geometries at brick boundaries On-grid geometries On-grid geometries On-grid geometries On-grid geometries r r Region of influence

Some Experimental Results

Little area benefit for using more than 10 unique bricks

• Few unique bricks allows for

macro regularity and silicon validation analogous to CLBs and bit cells

Trade-off between number

• f geometry patterns and

area/performance Ideally, regular fabric synthesis tool would determine this for each design in an application- specific manner

Firewire Controller

5000 10000 15000 20000 25000 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

Number of Bricks Area Estimate

1 2 3 4 5 6 7 8 9 10

• Avg. no. of Vias per Brick

Area

• No. of vias

Koggstone

5000 10000 15000 20000 25000 30000 35000 40000 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

Number of Bricks Area Estimate

1 2 3 4 5 6

• Avg. no. of Vias per Brick

Area

• No. of vias

Exploiting Regularity

• Logic regularity provides
• pportunities for new predictable

methodologies

1. Small library of primitives 2. Mapping into a set of configurable pre-defined bricks Factors f & f’ from F G1 & G2 are positive & negative cofactors with respect to function f

Ultimate Goal

• From synthesis we define the set of regular logic

bricks that cover the extracted logic modules

• From the fabrics level, perform shapes-level physical-

synthesis to construct configurable bricks

• Nano-scale constraints allow us to

simplify this shapes-level physical synthesis problem

• Can be optimized with simulation-

based printability modeling Automated layout

Further Considerations

Global effects and system-level issues

• Memory and logic compatibility
• Regular BEOL – structured routing
• Analog components

Cu thickness distribution

WLAN WCDMA GPS