Automata for Real-time Systems B. Srivathsan Chennai Mathematical - - PowerPoint PPT Presentation

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Dec 26, 2022 199 likes •483 views

Automata for Real-time Systems B. Srivathsan Chennai Mathematical Institute 1/26 In this lecture An academic case-study that investigates methods to build more reliable pacemakers 2/26 Lecture 10: Towards reliable pacemakers 3/26 References

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Automata for Real-time Systems

B. Srivathsan

Chennai Mathematical Institute

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SLIDE 2

In this lecture

An academic case-study that investigates methods to build more reliable pacemakers

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Lecture 10: Towards reliable pacemakers

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References

Modeling and verification of a dual chamber implantable pacemaker

Jiang, Pajic, Moarref, Alur, Mangharam. TACAS’12

Heart-on-a-chip: A closed-loop testing platform for implantable pacemakers

Jiang, Radhakrishnan, Sampath, Sarode, Mangharam. 2013 mlab.seas.upenn.edu

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Heart and pacemaker basics

Presentation of Zhihao Jiang (U Penn)

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Pacemaker software

In-built algorithms to detect and terminate various abnormal heart conditions

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Pacemaker software

In-built algorithms to detect and terminate various abnormal heart conditions At least 6 implanted medical devices were recalled in 2010 due to likely software defects

Killed by Code: Software Transparency in Implantable Medical Devices

Karen Sandler, Lysandra Ohrstrom, Laura Moy, Robert McVay 6/26

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Two possible solutions for more reliable devices:

◮ Model-based system/software design ◮ Closed-loop testing

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Model-based system/software design

Heart automaton Pacemaker automaton Simulink model Simulink model Heart on chip Pacemaker UPPAAL Simulink Testbench Verification Simulation Conformance testing

UPP2SF tool Code generation (Simulink is a commercial tool developed by Mathworks Inc.)

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Closed-loop testing

Heart ¡on ¡FPGA Boston ¡Scientific Pacemaker Analog ¡Interface

Heart on chip Pacemaker

Testbench Conformance testing

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Coming next: Modeling and verification of heart and pacemaker

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Heart as a timed automaton

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Abstract electrical conduction system of heart into nodes and paths

Picture credits: A Simulink hybrid heart model for quantitative verification of cardiac pacemakers Chen et. al. HSCC’13

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Refractory Time

Vout

ERP RRP Rest Rest Cond ERP RRP Rest Rest

Cond RRP t<=Trrp_max ERP t<=Terp_max temp Rest t<=Trest_max t>Trest_min t=0 Act_node? t=0 t>Trrp_min t=0 t>Terp_min t=0 Act_path! Act_node? t=0

Abstraction 1 N1

c

Cond Confmict t<=1 Double t1+t2<=Tcond_max Ante t1<=Tcond_max Retro t2<=Tcond_max Idle t1+t2>Tcond_min Act_node_1? Act_node_2? t>1 t1>Tcond_min Act_node_2! t2>Tcond_min Act_node_1! Act_path_2? t2=0 Act_path_1? t1=0

P1

Node Path Parameters Trest_max, Trrp_min, etc. chosen acc. to node placement and patient history

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Heart automaton H: N1 || P1 || N2 || P2|| . . . || Nk

Ni Node automaton Pi Path automaton k Number of nodes to which heart is abstracted || Parallel composition (asynchronous product construction)

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Pacemaker as a timed automaton

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Heart-pacemaker interaction

Heart

Pacemaker

Aget ! Vget ! VP ! AP !

1 2 3

N1. Act_Path! → Aget!
N2. Act_Path! → Vget

N1 node at atrial lead N2 node at ventricular lead

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Pacemaker timing cycles

1 2 3

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PVARP Aget? VS? VP? AS! AR! LRI AS? VS? VP? AP! AVI AS? VS? VP? VP! VS? URI VP? VRP Vget? VS! VP? (a) LRI component (b) AVI component (c) URI component (d) PVARP component (e) VRP component

Pacemaker automaton P: LRI || AVI || URI || PVARP || VRP

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Heart-pacemaker automaton: H || P

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An algorithm for Endless Loop Tachycardia

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Endless Loop Tachycardia (ELT)

Slides of Zhihao Jiang

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◮ ELT-detection: If VP-AS pattern within 500ms for at least 8 times ◮ ELT-termination: Increase PVARP to 500ms once

2 1 3

1 VPAS 2 ELTct 3 PVARP’

Pacemaker P1: LRI || AVI || URI || PVARP′ || VRP || ELTct || VPAS

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Is the modified pacemaker safe?

Question 1: Are 2 ventricular events within time?

secV wait_2nd wait_1st t=0 VP? Vget? VP? t=0 Vget? t=0 (a) Monitor PLRI test

Check in UPPAAL if in H || P1 || PLRItest, all paths satisfy PLRItest.t ≤ TLRI

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Is the modified pacemaker safe?

Question 2: Are 2 ventricular events very fast?

secV wait_vp wait_v Vget? t=0 t=0 VP? Vget? t=0 VP? t=0 (b) Monitor PURI test

Check in UPPAAL if in H || P1 || PURItest, all paths satisfy PURItest.t ≥ TURI

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Each time new algorithm is added, model it and check if basic safety properties are satisfied

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Take-home

◮ Model-based system/software design ◮ Closed-loop testing

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