Nanoscale III-V CMOS J. A. del Alamo Microsystems Technology - - PowerPoint PPT Presentation

Nanoscale III-V CMOS

• J. A. del Alamo

Microsystems Technology Laboratories Massachusetts Institute of Technology

Compound Semiconductor Week 2016 Toyama, Japan; June 26-30, 2016

Acknowledgements:

• Students and collaborators: D. Antoniadis, J. Lin, W. Lu, A. Vardi, X. Zhao
• Sponsors: Applied Materials, DTRA, KIST, Lam Research, Northrop Grumman,

NSF, Samsung

• Labs at MIT: MTL, EBL

Moore’s Law at 50: the end in sight?

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Moore’s Law

Moore’s Law = exponential increase in transistor density

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Intel microprocessors

2016: Intel 22-core Xeon Broadwell-E5 7.2B transistors

Moore’s Law

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?

How far can Si support Moore’s Law?

Transistor scaling  Voltage scaling  Performance suffers

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Transistor current density:

Goals:

• Reduced footprint with moderate short-channel effects
• High performance at low voltage

Intel microprocessors Intel microprocessors

Supply voltage:

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Moore’s Law: it’s all about MOSFET scaling

• 1. New device structures with improved scalability:
• 2. New materials with improved transport characteristics:

n-channel: Si  Strained Si  SiGe  InGaAs p-channel: Si  Strained Si  SiGe  Ge  InGaSb

Contents

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• 1. Self-aligned Planar InGaAs MOSFETs

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Lin, IEDM 2012, 2013, 2014 W Mo Lee, EDL 2014; Huang, IEDM 2014 selective MOCVD Sun, IEDM 2013, 2014 Chang, IEDM 2013 reacted NiInAs dry-etched recess implanted Si + selective epi

Self-aligned Planar InGaAs MOSFETs @ MIT

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Lin, IEDM 2012, 2013, 2014

Recess-gate process:

• CMOS-compatible
• Refractory ohmic contacts
• Extensive use of RIE

W Mo

0.0 0.1 0.2 0.3 0.4 0.5 0.0 0.2 0.4 0.6 0.8 1.0

Lg=20 nm Ron=224 m 0.4 V

Id (mA/m) Vds (V)

Vgs-Vt= 0.5 V

• Channel: In0.7Ga0.3As/InAs/In0.7Ga0.3As
• Gate oxide: HfO2 (2.5 nm, EOT~ 0.5 nm)

Highest performance InGaAs MOSFET

10

Lg=70 nm:

• Record gm,max = 3.45 mS/mm at Vds= 0.5 V
• Ron = 190 Ω.mm

Lin, EDL 2016

3.45 mS/m

Excess OFF-state current

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OFF-state current enhanced with Vds  Band-to-Band Tunneling (BTBT) or Gate-Induced Drain Leakage (GIDL)

Lin, IEDM 2013

• 0.6 -0.4 -0.2 0.0

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• 11

10

• 9

10

• 7

10

• 5

Lg=500 nm Vds=0.3~0.7 V step=50 mV

Id(A/m) Vgs (V)

Transistor fails to turn off:

Vds ↑

• 0.4 -0.2 0.0 0.2

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• 11

10

• 9

10

• 7

10

• 5

W/ BTBT+BJT W/O BTBT Vds=0.3~0.7 V step=50 mV

Id (A/m) Vgs (V)

Excess OFF-state current

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Lg↓  OFF-state current ↑  bipolar gain effect due to floating body

Lin, EDL 2014

• 0.6 -0.4 -0.2 0.0

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• 11

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• 9

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• 7

10

• 5

Lg=500 nm Vds=0.3~0.7 V step=50 mV

Id(A/m) Vgs (V)

• 0.6 -0.4 -0.2 0.0

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• 8

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• 7

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• 6

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• 5

10

• 4

500 nm 280 nm 120 nm T=200 K Vds=0.7 V

Id (A/m) Vgs-Vt (V)

Lg=80 nm

Vds ↑

Simulations

w/ BTBT+BJT w/o BTBT+BJT

Lg=500 nm

Lin, TED 2015

• 2. InGaAs FinFETs

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Intel Si Trigate MOSFETs

Bottom-up InGaAs FinFETs

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Si

Waldron, VLSI Tech 2014 Aspect-Ratio Trapping Fiorenza, ECST 2010 Epi-grown fin inside trench

Top-down InGaAs FinFETs

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Kim, IEDM 2013

60 nm

dry-etched fins Radosavljevic, IEDM 2010

20 40 60 0.0 0.5 1.0 1.5 2.0

1.8 1 0.8 0.57

InGaAs FinFETs

5.3 4.3

Si FinFETs

gm[mS/m] Wf [nm]

0.63 0.6 0.23 0.66 1 0.18

InGaAs FinFETs: gm

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Thathachary, VLSI 2015

gm normalized by width of gate periphery

• Narrowest InGaAs FinFET fin: Wf=15 nm
• Best channel aspect ratio of InGaAs FinFET: 1.8
• gm much lower than planar InGaAs MOSFETs

Oxland, EDL 2016 Radosavljevic, IEDM 2011 Kim, IEDM 2013 Natarajan, IEDM 2014

channel aspect ratio

InGaAs FinFETs @ MIT

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Vardi, DRC 2014, EDL 2015, IEDM 2015

Key enabling technologies: BCl3/SiCl4/Ar RIE + digital etch

• Sub-10 nm fin width
• Aspect ratio > 20
• Vertical sidewalls

InGaAs FinFETs @ MIT

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Vardi, VLSI Tech 2016

• CMOS compatible process
• Mo contact-first process
• Fin etch mask left in place  double-gate MOSFET

At VDS=0.5 V:

• gm=1.4 mS/µm
• Ron=170 Ω.µm
• Ssat=170 mV/dec

InGaAs FinFETs @ MIT

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Vardi, VLSI Tech 2016 Lg=30 nm, Wf=22 nm, Hc=40 nm (AR=1.8):

0.0 0.2 0.4 0.6 0.8 1.0 200 400 600 800 1000 1200

VGS= 0.75V 0.5 0.25

• 0.25

Id [Am] VDS [V]

• 0.5
• 0.6 -0.4 -0.2

0.0 0.2 0.4 0.6 0.8 200 400 600 800 1000 Wf=22 nm Lg=30 nm VDS=500mV

VGS [V] Id [Am]

400 800 1200 1600

gm [Sm

• 0.6
• 0.4
• 0.2

0.0 0.2 0.4 0.6 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 DIBL=220 mV/V

VGS [V] Id [Am]

Wf=22 nm Lg=30 nm VDS=500 mV 50 mV S=140 mV/dec 170

Hc

Current normalized by 2xHc

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• 0.6
• 0.4
• 0.2

0.0 0.2 0.4 0.6 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5 Wf=7 nm Lg=20 nm VDS=500 mV

VGS [V] Id [Am]

50 mV S=120 mV/dec DIBL~150

0.0 0.2 0.4 0.6 0.8 1.0 10 20 30 40 VGS= 0.75 V 0.5 0.25

• 0.25

Id [Am] VDS [V]

Most aggressively scaled FinFET

Lg=20 nm, Wf=7 nm, Hc=40 nm (AR=5.7): Vardi, VLSI Tech 2016 At VDS=0.5 V:

• gm=170 µS/µm
• Ron=4 kΩ.µm
• Ssat=130 mV/dec

InGaAs FinFETs: gm benchmarking

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gm normalized by width of gate periphery:

• First InGaAs FinFETs with Wf<10 nm
• Severe gm degradation for thin Wf  sidewall roughness?

Hc Wf

Vardi, VLSI Tech 2016

Hc

Double gate Trigate

20 40 60 0.0 0.5 1.0 1.5 2.0

1.8 1 0.8 0.57 5.7 3.3 2.3 1.8

InGaAs FinFETs

5.3 4.3

Si FinFETs

gm[mS/m] Wf [nm]

0.63 0.6 0.23 0.66 1 0.18

Latest results

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Record results for InGaAs FinFETs with Wf < 25 nm

• Scaled gate oxide: HfO2 with EOT=0.6 nm
• Attention to line-edge roughness

20 40 60 0.0 0.5 1.0 1.5 2.0

1.8 1 0.8 0.57 5.7 3.3 2.3 1.8

InGaAs FinFETs

5.3 4.3

Si FinFETs

gm[mS/m] Wf [nm]

0.63 0.6 0.23 0.66 1 0.18

Latest!

Vardi, submitted 2016

InGaAs FinFETs: gm benchmarking

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gm normalized by fin width (FOM for density):

• Doubled gm over earlier InGaAs FinFETs
• Still far below Si FinFETs  poor sidewall charge control

Vardi, submitted 2016

20 40 60 5 10 15 20

1.8 1 EOT=1 nm (HfO2/Al2O3) EOT=0.6 nm (HfO2) 0.57 0.8 5.7 3.32.31.8

InGaAs FinFETs

5.3 4.3

Si FinFETs

gm/Wf [mS/m] Wf [nm]

0.63 0.6 0.23 0.66 1 0.18

Hc Wf Wf Hc

Impact of fin width on VT

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• Strong VT sensitivity for Wf < 10 nm; much worse than Si
• Due to quantum effects

InGaAs doped-channel FinFETs: 50 nm thick, ND~1018 cm-3

Vardi, IEDM 2015

T=90K

• 3. Nanowire InGaAs MOSFETs

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Waldron, EDL 2014 Tomioka, Nature 2012 Persson, EDL 2012

• Nanowire MOSFET: ultimate scalable transistor
• Vertical NW: uncouples footprint scaling from Lg and Lc scaling

Tanaka, APEX 2010

InGaAs Vertical Nanowires on Si by direct growth

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Björk, JCG 2012 Selective-Area Epitaxy Au seed Vapor-Solid-Liquid (VLS) Technique InAs NWs on Si by SAE Riel, MRS Bull 2014

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InGaAs VNW MOSFETs by top-down approach @ MIT

• Sub-20 nm NW diameter
• Aspect ratio > 10
• Smooth sidewalls

Zhao, EDL 2014 Key enabling technologies:

• RIE = BCl3/SiCl4/Ar chemistry
• Digital Etch (DE) =

O2 plasma oxidation H2SO4 oxide removal

15 nm 240 nm

• 0.4
• 0.2

0.0 0.2 0.4 100 200 300 400 500 600 700 Vgs(V)

Vds=0.5 V

gm,pk(S/m)

NW-MOSFET I-V characteristics: D=40 nm

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Single nanowire MOSFET:

• Lch= 80 nm
• 3 nm Al2O3 (EOT = 1.5 nm)
• gm,pk=620 μS/μm @ VDS=0.5 V
• Ssat=110 mV/dec @ VDS=0.5 V
• Approaches best bottom-up devices

[Berg, IEDM 2015]

0.0 0.1 0.2 0.3 0.4 0.5 50 100 150 200 250 300 350

Bottom electrode as the source (BES)

Vgs=-0.2 V to 0.7 V in 0.1 V step Vds (V)

Id A/m)

Zhao, 2016 (submitted)

• 0.4
• 0.2

0.0 0.2 0.4 10

• 9

10

• 8

10

• 7

10

• 6

10

• 5

10

• 4

Vds=0.5 V

Vgs(V) Id (A/m)

Vds=0.05 V

S=98 mV/dec, Vds=0.05 V S=110 mV/dec, Vds=0.5 V DIBL = 177 mV/V

Self-aligned Bottom-up InAs NW-MOSFETs

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VNW MOSFET array:

• VLS growth
• D=28 nm
• Lch= 190 nm
• gm,pk=850 μS/μm @ VDS=0.5 V
• Ssat=154 mV/dec @ VDS=0.5 V

Berg, IEDM 2015

How are we doing in terms of short-channel effects?

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del Alamo, J-EDS 2016 Slin: linear subthreshold swing Lg= gate length λc= electrostatic scaling length: f(tox, tch) Ideal scaling

FinFET Planar-MOSFET VNW MOSFET

• Reasonable scaling behavior but…
• Excessive Dit

• 4. InGaSb p–type MOSFETs

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Nainani, IEDM 2010

Planar InGaSb MOSFET demonstrations:

Takei, Nano Lett. 2012

InGaSb p–type FinFETs @ MIT

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Lu, IEDM 2015

Key enabling technology:

• BCl3/N2 RIE
• [digital etch under development]

15 nm fins, AR>13 20 nm fins, 20 nm spacing

• Smallest Wf = 15 nm
• Aspect ratio >10
• Fin angle > 85°
• Dense fin patterns

InGaSb p-type FinFETs

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Lu, IEDM 2015

• Fin etch mask left in place  double-gate MOSFET
• Channel: 10 nm In0.27Ga0.73Sb (compressively strained)
• Gate oxide: 4 nm Al2O3 (EOT=1.8 nm)

InGaSb FinFET I-V characteristics

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• Lg = 100 nm, Wf = 30 nm (AR=0.33)
• Normalized by conducting gate periphery

Lu, IEDM 2015

0.01 0.1 1 10 100 10 100

Yuan, 2013 [7] Nainani, 2010 [8] Chu, 2014 [11] Xu, 2011 [12] Nagaiah, 2011 [13]

In0.36Ga0.64Sb GaSb

gm (S/m) Lg (m)

This work (FinFET) In0.27Ga0.73Sb GaSb In0.35Ga0.65Sb In0.2Ga0.8Sb

Planar MOSFETs

• First InGaSb FinFET
• Peak gm approaches best InGaSb planar MOSFETs
• Poor turn off

Co-integration of SiGe p-MOSFETs and InGaAs MOSFETs on SOI

35

InGaAs n-MOSFET

Czornomaz, VLSI Tech 2016

SiGe p-MOSFET 6T-SRAM

SiGe InGaAs Si SiO2

Confined Epitaxial Lateral Overgrowth

Conclusions

1. Great recent progress on planar, fin and nanowire InGaAs MOSFETs 2. Planar and multigate InGaAs MOSFETs exhibit nearly ideal electrostatic scaling behavior but poor Dit 3. Device performance still lacking for multigate designs 4. P-type InGaSb MOSFETs in their infancy 5. Many issues to work out:

sub-10 nm fin/nanowire fabrication, self-aligned contacts, device asymmetry, introduction of mechanical stress, VT control, sidewall roughness, device variability, BTBT and parasitic HBT gain, trapping, self- heating, reliability, NW survivability, co-integration on n- and p-channel devices on Si, …

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A lot of work ahead but… exciting future for III-V electronics