[PPT] - R I S C - V s u p p o r t i n O T A WA : V a l PowerPoint Presentation

SLIDE 1

R I S C

V

s u p p

r

t i n O T A WA : V a l i d a t i

n
f

t h e I S A d e s c r i p t i

n

E m m a n u e l C a u s s é , H u g u e s C a s s é , P a s c a l S a i n r a t , T R A C E S – I R I T – U n i v e r s i t y

f

T

u

l

u

s e P a r i s 1

2

/ 1 / 2 1 9

SLIDE 2

2

I n t r

d

u c t i

n
s

t a t i c a n a l y s i s t

l

s

n

m a c h i n e c

d

e ( WC E T )

– d

e c

d

i n g a n d p r

c

e s s i n g m a c h i n e c

d

e

– s

u

n d m

d

e l

f

t h e I n s t r u c t i

n

S e t A r c h i t e c t u r e ( I S A )

a

p p l i e d t

R

I S C

V

– A

r c h i t e c t u r e D e s c r i p t i

n

L a n g u a g e ( A D L ) m

d

e l

– “

v e r i f i e d ” b y c

s

i m u l a t i

n

SLIDE 3

3

P r e s e n t a t i

n

O u t l i n e

I

n t r

d

u c t i

n
I

S S g e n e r a t i

n
I

S A v a l i d a t i

n
T
w

a r d s s t a t i c a n a l y s i s

C
n

c l u s i

n

SLIDE 4

4

I S S G e n e r a t i

n

Wo r k

risc.nmp gliss2 riscv-sim riscv-disasm prog.elf (risc-v)

Architecture Description Language (SimNML) Instruction Set Simulator generator ISS simulator ISS disassembler

SLIDE 5

5

I n s t r u c t i

n

S e t A r c h i t e c t u r e D e s c r i p t i

n

S i m N M L

– t

y p e s

– r

e g i s t e r s

– m

e m

r

i e s

– o

p e r a t i

n

s

– m

d

e s

[ F r e e r i c k s – 1 9 9 1 ]

risc.nml type byte = int ( 8) type word = int (32) type address = card(32) mem M [32, byte] mem M32 [32, word] alias = M reg PC [ 1, address] is_pc = 1 reg NPC [ 1, address] reg R [32, word] reg F [32, float(23,9)]

SLIDE 6

6

Mo d e d e s c r i p t i

n
a

d d r e s s i n g m

d

e s

s

p e c i a l f

r

m a t ( r e g i s t e r )

s

p e c i a l c a l c u l a t i

n

( h a r d w i r e d r e g i s t e r )

.

. .

risc.nml mode reg_t (r: index) = r syntax = switch ( r ) { case 0: "zero" case 1: "ra" case 2: "sp" case 3: "gp" case 4: "tp … } image = format ( "%5b", r )

SLIDE 7

7

O p e r a t i

n

d e s c r i p t i

n
i

m a g e – b i n a r y

s

y n t a x – a s s e m b l y

a

c t i

n

– i

m p e r a t i v e l a n g u a g e

– b

i t

r

i e n t e d

– f

r

m a l l y d e f i n e d

– s

y n t h e s i z a b l e [ B a s u , M

n

a

2

3 ]

– c

l

s

e t

h

a n d b

k

p s e u d

c
d

e ( l e s s e r r

r
p

r

n

e ? )

risc.nml

p addi(imm: int(12), s: reg_t, d: reg_t)

syntax = format("addi %s, %s, %d", d, s, imm) image = format("%12b %s 000 %s 0010011", i, s, d) action = { if d != 0 then R[d] = R[s] + imm; endif; }

SLIDE 8

8

O u r i m p l e m e n t a t i

n
n
p

s e u d

c
d

e i n [ T h e R I S C

V

I n s t r u c t i

n

S e t M a n u a l , V

l

u m e I : U s e r

L

e v e l I S A , V e r s i

n

2 . – 2 1 4 ]

s

e v e r a l c

n

t r i b u t

r

s

– M

. F r i e b – A u g s b u r g U n i v e r s i t y ( i n i t i a l i m p l e m e n t a t i

n

)

– E

. C a u s s é – U n i v e r s i t y

f

T

u

l

u

s e

– P

. S a i n r a t – U n i v e r s i t y

f

T

u

l

u

s e

o

v e r a l l r e s u l t s

– 1

7 4 i n s t r u c t i

n

s 3 2

b

i t , 1 3 i n s t r u c t i

n

s 6 4

b

i t

– e

x t e n s i

n

s – 3 2

b

i t ( I , M , A , F , D , C ) , 6 4

b

i t ( I )

– m

i s s i n g – 2 i n s t r u c t i

n

s 3 2

b

i t , 2 5 i n s t r u c t i

n

s 6 4

b

i t

SLIDE 9

9

R I S C

V

F r e a k s

bbb11

31 16 15

aa

15 Compact extension: 32-bit 16-bit 16-bit if aa = 11 bbb ≠ 111

risc.nml

let gliss_isize = “32,16”

p c_add(dest: enum(1..31), src2: enum(1..31))

image = format("100 1 %5b %5b 10",dest,src2) ...

p add(src2: reg_t, src1: reg_t, dest: reg_t)

image = format("0000000 %s %s 000 %s 0110011", src2, src1, dest) ...

Already supported by GLISS2 for ARM Thumb-2, PowerPC VLE , TriCore, Star12X, x86.

SLIDE 10

1

I m p l e m e n t a t i

n

a c t i v i t y

Adding a new instruction Understanding The handbook Writing the binary encoding Writing the disassembly Writing the action Fixing an existing instruction re-read the action → fix obvious mistakes examine the simulation → detect anomalies Wh a t ’ s a b

u

t t h e v a l i d i t y

f

t h e r e s u l t ?

SLIDE 11

1 1

P r e s e n t a t i

n

O u t l i n e

I

n t r

d

u c t i

n
I

S S g e n e r a t i

n
I

S A v a l i d a t i

n
T
w

a r d s s t a t i c a n a l y s i s

C
n

c l u s i

n

SLIDE 12

1 2

C

s

i m u l a t i

n

ISS Simulator Validator Third-party execution source Real hardware Other simulator

1041e ld ra,8(sp) 10420 ld s0,0(sp) 10422 addi sp,sp,16 10424 ret binary_search: 10426 addi sp,sp,-48 10428 sd s0,40(sp) 1042a addi s0,sp,48 1042c mv a5,a0 1042e sw a5,-36(s0) 10432 sw zero,-24(s0) 10436 li a5,14 10438 sw a5,-28(s0) 1043c li a5,-1 1041e ld ra,8(sp) 10420 ld s0,0(sp) 10422 addi sp,sp,16 10424 ret binary_search: 10426 addi sp,sp,-48 10428 sd s0,40(sp) 1042a addi s0,sp,48 1042c mv a5,a0 1042e sw a5,-36(s0) 10432 sw zero,-24(s0) 10436 li a5,14 10438 sw a5,-28(s0) 1043c li a5,-1

pc = pc ra = ra sp = sp gp = gp … t5 = t5 t6 = t6

SLIDE 13

1 3

F

r

R I S C

V

riscv-sim riscv validator validator template riscv-gdb

penocd

spike tuned by hand → gliss2 easy to connect with a real hardware

SLIDE 14

1 4

E x p e r i m e n t a t i

n
b

e n c h m a r k s

– r

i s c v

t

e s t s ( g i t h u b ) – ( c ) U n i v e r s i t y

f

C a l i f

r

n i a

– 1

t e s t / i n s t r u c t i

n

( 2 1 7 t e s t s – ~ 9 5 l i n e s

f

c

d

e )

r

e s u l t s

– s

l

w

– 5

6

x ( d

e

s n ’ t m a t t e r )

– >

1 – f i x e s

– s

m

e i n s t r u c t i

n

s c a n ’ t b e t e s t e d ! ( i n t e r n a l / s y s t e m – 1 3 i n s t r u c t i

n

s )

SLIDE 15

1 5

Me m

r

y C

m

p a r i s

n

risc.nmp gliss2 riscv-sim riscv-sim riscv-sim

performances hardware simulation memory spy

risc-validator

address + value register / value

execution source

register memory address

SLIDE 16

1 6

P a r t i a l c

n

c l u s i

n
I

t ’ s n

t

a p r

f

!

We

t e s t i f 2 m a c h i n e s a r e e q u i v a l e n t …

E

r r

r

= m a c h i n e 1 ? m a c h i n e 2 ? B

t

h ?

B

u t w e i m p r

v

e c

n

f i d e n c e i n

u

r R I S C

V

A D L d e s c r i p t i

n

( n

t

s

b

a d )

SLIDE 17

1 7

P r e s e n t a t i

n

O u t l i n e

I

n t r

d

u c t i

n
I

S S g e n e r a t i

n
I

S A v a l i d a t i

n
T
w

a r d s s t a t i c a n a l y s i s

C
n

c l u s i

n

SLIDE 18

1 8

B i n a r y s t a t i c a n a l y s e r : O T A WA

risc.nmp gliss2 riscv-decoder riscv-disasm riscv-regs gliss-used-regs gliss-attr riscv-branch riscv-kind riscv-sem branch.nmp kind.nmp sem.nmp OTAWA Loader OTAWA Framework (WCET)

SLIDE 19

1 9

V e r i f i c a t i

n

e x p e r i m e n t ( T r i C

r

e )

[ W.

T

. S u n & a l . V a l i d a t i n g S t a t i c W C E T A n a l y s i s : A M e t h

d

a n d I t s A p p l i c a t i

n

. WC E T ’ 1 9 ]

T

r i C

r

e I n s t r u c t i

n

S e t ( ~ 3 3 i n s t r u c t i

n

s )

c
s

i m u l a t i

n

– G

L I S S I S S / T S I M

– 6

7 f i x e s

d

a t a f l

w

a n a l y s i s

– O

T A WA : m a c h i n e i n s t r u c t i

n

s e m a n t i c i n s t r u c t i

n

s ( I S A i n d e p e n d e n t )

– s

i m u l a t i

n

s t a t e s a b s t r a c t s t a t e ?

– 7

1 f i x e s

p

a r t i a l c

v

e r a g e

f

i n s t r u c t i

n

s e t c

m

p i l e r

SLIDE 20

2

O u r

b

j e c t i v e

risc.nmp gliss2 riscv-decoder riscv-disasm riscv-regs gliss-used-regs gliss-gen riscv-branch riscv-kind riscv-sem OTAWA Loader OTAWA Framework (WCET) golden model

SLIDE 21

2 1

Wh y R I S C

V

?

s

i m p l e a n d s m a l l i n s t r u c t i

n

s e t

g l i s s

g

e n d e m

n

s t r a t

r

e a s i e r t

e

x p e r i m e n t

o

p e n “ s t a n d a r d ”

– “

p

e n m i c r

a

r c h i t e c t u r e ” ?

– f

u l l v i s i b i l i t y

f

i n t e r n a l s

– b

e t t e r t i m i n g m

d

e l f

r

WC E T c a l c u l a t i

n

SLIDE 22

2 2

P r e s e n t a t i

n

O u t l i n e

I

n t r

d

u c t i

n
I

S S g e n e r a t i

n
I

S A v a l i d a t i

n
T
w

a r d s s t a t i c a n a l y s i s

C
n

c l u s i

n

SLIDE 23

2 3

C

n

c l u s i

n
V

a l i d a t

r

– i

m p r

v

e c

n

f i d e n c e i n R I S C

V

A D L m

d

e l

– p

r

t a b l e t

d

i f f e r e n t a r c h i t e c t u r e s

F

u t u r e . . .

– b

e n c h m a r k s e l e c t i

n

t

i

m p r

v

e c

v

e r a g e ( a u t

m

a t i c g e n e r a t i

n

? )

– i

m p l e m e n t a n d e x p e r i m e n t g l i s s

g

e n

– WC

E T f

r

R I S C

V

w i t h

p

e n m i c r

a

r c h i t e c t u r e

SLIDE 24

2 4

A n y q u e s t i

n

?

I n s t r u c t i

n

S e t h t t p s : / / g i t h u b . c

m