Systems Delays (contd) Shankar Balachandran* Associate Professor, - - PowerPoint PPT Presentation

Shankar Balachandran* Associate Professor, CSE Department Indian Institute of Technology Madras

*Currently a Visiting Professor at IIT Bombay

Digital Circuits and Systems

Spring 2015 Week 5 Module 25

Delays (contd)

Sequential Element Delays

 More complicated than combinational logic elements  Two components

 Setup and Hold time  Intrinsic propagation delays

Delays 2

Delays 3

Setup and Hold Times

 Setup time, tsu, is the time period prior to the clock

becoming active (edge or level) during which the flip-flop inputs must remain stable.

 Hold time, th, is the time after the clock becomes inactive

during which the flip-flop inputs must remain stable.

 Setup time and hold time define a window of time during

which the flip-flop inputs cannot change – quiescent interval.

Delays 4

Propagation Delay

 Propagation delay, tpHL and tpLH , has the same

meaning as in combinational circuit – beware propagation delays usually will not be equal for all input to output pairs. There can be two propagation delays: tC-

Q (clock→Q delay) and tD-Q (data→Q delay).

 For a level or pulse triggered latch:

 Data input should remain stable till the clock becomes inactive.  Clock should remain active till the input change is propagated to

Q output. That is, active period of the clock, tw > max {tpLH, tpHL}

Delays 5

Latch & Flip-flop Timing Parameters

Delays 6

Latch and Flip-flop Timings

CLK D Q Q

Flip-flop Latch tsu th tC-Q tsu th tC-Q tsu th tC-Q tD-Q

Delays 7

More Precise FF Setup and Hold Times

CLK D Q t t t

Sampling Window

50 100 150 200 250 300 350

• 200
• 150
• 100
• 50

50 100 150 200

Data-Clk [ps] Clk-Output [ps] Setup Hold

Minimum Data-Output

Delays 8

Characterizing Timing

• Setup time, hold time
• Propagation delays

tC-Q tC-Q tD-Q Flip-Flop Latch tD-C tD-C

End of Week 5: Module 25

Thank You

Delays 9